Ashenden, Peter J.
VHDL-2008 : just the new stuff / Peter J. Ashenden, Jim Lewis. - Amsterdam ; Boston : Elsevier/Morgan Kaufmann, c2008. - x, 244 p. ; 24 cm. - The Morgan Kaufmann series in systems on silicon . - Morgan Kaufmann series in systems on silicon. .
Includes index.
Enhanced Generics Generic Types Generic Lists in Packages Local Packages Generic Lists in Subprograms Generic Subprograms Uninstantiated Methods in Protected Types Generic Packages Use Case: Generic Memories Other Major Features External Names Force and Release Context Declarations Integrated PSL IP Encryption Key Exchange VHDL Procedural Interface (VHPI) Direct Binding Tabular Registration and Indirect Binding Registration of Applications and Libraries Type System Changes Unconstrained Element Types Composite Types Subtype Indications and Constraints Use of Composite Subtypes Variable and Signal Declarations Constant Declarations Attribute Specifications Allocated Objects Interface Objects Summary: Determining Array Index Ranges Type Conversions Alias Declarations and Subtype Attributes Resolved Composite Subtypes Resolved Elements New and Changed Operations Array/Scalar Logical Operations Array/Scalar Addition Operators Logical Reduction Operators Condition Operator Matching Relational Operators Maximum and Minimum Mod and Rem for Physical Types Shift Operations Strength Reduction and 'X' Detection New and Changed Statements Conditional and Selected Assignments Sequential Signal Assignments Forcing Assignments Variable Assignments Matching Case Statements Matching Selected Assignments If and Case Generate Configuration of If and Case Generate Modeling Enhancements Signal Expressions in Port Maps All Signals in Sensitivity List Reading Out-Mode Ports and Parameters Slices in Aggregates Bit-String Literals Improved I/O The To_String Functions Predefined To_string Functions Overloaded To_string Functions The To_ostring and To_hstring Functions The Justify Function Newline Formatting Read and Write Operations The Tee Procedure The Flush Procedure Standard Packages The Std_logic_1 164 Package The Numeric_bit and Numeric_std Packages The Numeric Unsigned Packages The Fixed-Point Math Packages The Floating-Point Math Packages The Standard Package The Env Package Operator Overloading Summary Conversion Function Summary Strength Reduction Function Summary Miscellaneous Changes Referencing Generics in Generic Lists Function Return Subtype Qualified Expression Subtype Type Conversions Case Expression Subtype Subtypes for Port and Parameter Actuals Static Composite Expressions Static Ranges Use Clauses, Types, and Operations Hiding of Implicit Operations Multidimensional Array Alias Others in Aggregates Attribute Specifications in Package Bodies Attribute Specification for Overloaded Subprograms Integer Expressions in Range Bounds Action on Assertion Violations 'Path_Name and 'Instance_Name Non-Nesting of Architecture Region Purity of Now Delimited Comments Tool Directives New Reserved Words Replacement Characters Object-Oriented Class Types Standard Components Library Randomization Functional Coverage Alternatives Getting Involved 1 1 -- 1.1 1 -- 1.2 6 -- 1.3 11 -- 1.4 15 -- 1.5 21 -- 1.5.1 32 -- 1.6 36 -- 1.7 43 -- 2 53 -- 2.1 53 -- 2.2 63 -- 2.3 67 -- 2.4 70 -- 2.5 77 -- 2.5.1 96 -- 2.6 97 -- 2.6.1 97 -- 2.6.2 99 -- 2.6.3 101 -- 3 103 -- 3.1 103 -- 3.1.1 103 -- 3.1.2 107 -- 3.1.3 109 -- 110 -- 110 -- 111 -- 111 -- 112 -- 117 -- 118 -- 119 -- 122 -- 3.2 123 -- 4 127 -- 4.1 127 -- 4.2 129 -- 4.3 130 -- 4.4 132 -- 4.5 133 -- 4.6 138 -- 4.7 140 -- 4.8 141 -- 4.9 142 -- 5 143 -- 5.1 143 -- 5.1.1 143 -- 5.1.2 146 -- 5.1.3 147 -- 5.2 149 -- 5.2.1 150 -- 5.3 151 -- 5.3.1 155 -- 6 159 -- 6.1 159 -- 6.2 161 -- 6.3 162 -- 6.4 166 -- 6.5 167 -- 7 169 -- 7.1 169 -- 7.1.1 170 -- 7.1.2 171 -- 7.1.3 172 -- 7.2 173 -- 7.3 173 -- 7.4 174 -- 7.5 177 -- 7.6 178 -- 8 179 -- 8.1 179 -- 8.2 180 -- 8.3 182 -- 8.4 182 -- 8.5 186 -- 8.6 191 -- 8.7 192 -- 8.8 193 -- 8.9 196 -- 8.10 204 -- 9 207 -- 9.1 207 -- 9.2 208 -- 9.3 209 -- 9.4 209 -- 9.5 211 -- 9.6 212 -- 9.7 213 -- 9.8 214 -- 9.9 215 -- 9.10 216 -- 9.11 217 -- 9.12 217 -- 9.13 219 -- 9.14 219 -- 9.15 220 -- 9.16 221 -- 9.17 221 -- 9.18 223 -- 9.19 223 -- 9.20 224 -- 9.21 225 -- 9.22 225 -- 9.23 226 -- 10.1 229 -- 10.1.1 232 -- 10.2 232 -- 10.3 235 -- 10.4 235 -- 10.5 235.
9780123742490 (pbk. : alk. paper) 0123742498 (pbk. : alk. paper)
2007039499
VHDL (Computer hardware description language)
TK7885.7 / .A846 2008
621.39/2
VHDL-2008 : just the new stuff / Peter J. Ashenden, Jim Lewis. - Amsterdam ; Boston : Elsevier/Morgan Kaufmann, c2008. - x, 244 p. ; 24 cm. - The Morgan Kaufmann series in systems on silicon . - Morgan Kaufmann series in systems on silicon. .
Includes index.
Enhanced Generics Generic Types Generic Lists in Packages Local Packages Generic Lists in Subprograms Generic Subprograms Uninstantiated Methods in Protected Types Generic Packages Use Case: Generic Memories Other Major Features External Names Force and Release Context Declarations Integrated PSL IP Encryption Key Exchange VHDL Procedural Interface (VHPI) Direct Binding Tabular Registration and Indirect Binding Registration of Applications and Libraries Type System Changes Unconstrained Element Types Composite Types Subtype Indications and Constraints Use of Composite Subtypes Variable and Signal Declarations Constant Declarations Attribute Specifications Allocated Objects Interface Objects Summary: Determining Array Index Ranges Type Conversions Alias Declarations and Subtype Attributes Resolved Composite Subtypes Resolved Elements New and Changed Operations Array/Scalar Logical Operations Array/Scalar Addition Operators Logical Reduction Operators Condition Operator Matching Relational Operators Maximum and Minimum Mod and Rem for Physical Types Shift Operations Strength Reduction and 'X' Detection New and Changed Statements Conditional and Selected Assignments Sequential Signal Assignments Forcing Assignments Variable Assignments Matching Case Statements Matching Selected Assignments If and Case Generate Configuration of If and Case Generate Modeling Enhancements Signal Expressions in Port Maps All Signals in Sensitivity List Reading Out-Mode Ports and Parameters Slices in Aggregates Bit-String Literals Improved I/O The To_String Functions Predefined To_string Functions Overloaded To_string Functions The To_ostring and To_hstring Functions The Justify Function Newline Formatting Read and Write Operations The Tee Procedure The Flush Procedure Standard Packages The Std_logic_1 164 Package The Numeric_bit and Numeric_std Packages The Numeric Unsigned Packages The Fixed-Point Math Packages The Floating-Point Math Packages The Standard Package The Env Package Operator Overloading Summary Conversion Function Summary Strength Reduction Function Summary Miscellaneous Changes Referencing Generics in Generic Lists Function Return Subtype Qualified Expression Subtype Type Conversions Case Expression Subtype Subtypes for Port and Parameter Actuals Static Composite Expressions Static Ranges Use Clauses, Types, and Operations Hiding of Implicit Operations Multidimensional Array Alias Others in Aggregates Attribute Specifications in Package Bodies Attribute Specification for Overloaded Subprograms Integer Expressions in Range Bounds Action on Assertion Violations 'Path_Name and 'Instance_Name Non-Nesting of Architecture Region Purity of Now Delimited Comments Tool Directives New Reserved Words Replacement Characters Object-Oriented Class Types Standard Components Library Randomization Functional Coverage Alternatives Getting Involved 1 1 -- 1.1 1 -- 1.2 6 -- 1.3 11 -- 1.4 15 -- 1.5 21 -- 1.5.1 32 -- 1.6 36 -- 1.7 43 -- 2 53 -- 2.1 53 -- 2.2 63 -- 2.3 67 -- 2.4 70 -- 2.5 77 -- 2.5.1 96 -- 2.6 97 -- 2.6.1 97 -- 2.6.2 99 -- 2.6.3 101 -- 3 103 -- 3.1 103 -- 3.1.1 103 -- 3.1.2 107 -- 3.1.3 109 -- 110 -- 110 -- 111 -- 111 -- 112 -- 117 -- 118 -- 119 -- 122 -- 3.2 123 -- 4 127 -- 4.1 127 -- 4.2 129 -- 4.3 130 -- 4.4 132 -- 4.5 133 -- 4.6 138 -- 4.7 140 -- 4.8 141 -- 4.9 142 -- 5 143 -- 5.1 143 -- 5.1.1 143 -- 5.1.2 146 -- 5.1.3 147 -- 5.2 149 -- 5.2.1 150 -- 5.3 151 -- 5.3.1 155 -- 6 159 -- 6.1 159 -- 6.2 161 -- 6.3 162 -- 6.4 166 -- 6.5 167 -- 7 169 -- 7.1 169 -- 7.1.1 170 -- 7.1.2 171 -- 7.1.3 172 -- 7.2 173 -- 7.3 173 -- 7.4 174 -- 7.5 177 -- 7.6 178 -- 8 179 -- 8.1 179 -- 8.2 180 -- 8.3 182 -- 8.4 182 -- 8.5 186 -- 8.6 191 -- 8.7 192 -- 8.8 193 -- 8.9 196 -- 8.10 204 -- 9 207 -- 9.1 207 -- 9.2 208 -- 9.3 209 -- 9.4 209 -- 9.5 211 -- 9.6 212 -- 9.7 213 -- 9.8 214 -- 9.9 215 -- 9.10 216 -- 9.11 217 -- 9.12 217 -- 9.13 219 -- 9.14 219 -- 9.15 220 -- 9.16 221 -- 9.17 221 -- 9.18 223 -- 9.19 223 -- 9.20 224 -- 9.21 225 -- 9.22 225 -- 9.23 226 -- 10.1 229 -- 10.1.1 232 -- 10.2 232 -- 10.3 235 -- 10.4 235 -- 10.5 235.
9780123742490 (pbk. : alk. paper) 0123742498 (pbk. : alk. paper)
2007039499
VHDL (Computer hardware description language)
TK7885.7 / .A846 2008
621.39/2