| 000 -LEADER |
|---|
| fixed length control field |
07817cam a2200325 a 4500 |
| 001 - CONTROL NUMBER |
|---|
| control field |
u8871 |
| 003 - CONTROL NUMBER IDENTIFIER |
|---|
| control field |
SA-PMU |
| 005 - DATE AND TIME OF LATEST TRANSACTION |
|---|
| control field |
20210418125044.0 |
| 008 - FIXED-LENGTH DATA ELEMENTS--GENERAL INFORMATION |
|---|
| fixed length control field |
070509s2007 njua b 001 0 eng |
| 010 ## - LIBRARY OF CONGRESS CONTROL NUMBER |
|---|
| LC control number |
2011377174 |
| 040 ## - CATALOGING SOURCE |
|---|
| Original cataloging agency |
UKM |
| Language of cataloging |
eng |
| Transcribing agency |
UKM |
| Modifying agency |
UMC |
| -- |
VRC |
| -- |
UBC |
| -- |
DEBBG |
| -- |
OCL |
| -- |
DLC |
| -- |
BDX |
| -- |
HDC |
| -- |
UKMGB |
| -- |
OCLCF |
| 020 ## - INTERNATIONAL STANDARD BOOK NUMBER |
|---|
| International Standard Book Number |
9780470127421 (pbk.) |
| 020 ## - INTERNATIONAL STANDARD BOOK NUMBER |
|---|
| International Standard Book Number |
0470127422 (pbk.) |
| 035 ## - SYSTEM CONTROL NUMBER |
|---|
| System control number |
(OCoLC)190776332 |
| 042 ## - AUTHENTICATION CODE |
|---|
| Authentication code |
ukblcatcopy |
| 050 #4 - LIBRARY OF CONGRESS CALL NUMBER |
|---|
| Classification number |
TK7874.75 |
| Item number |
.X55 2008 |
| 082 04 - DEWEY DECIMAL CLASSIFICATION NUMBER |
|---|
| Classification number |
621.395 |
| Edition number |
22 |
| 100 1# - MAIN ENTRY--PERSONAL NAME |
|---|
| Personal name |
Xiu, Liming. |
| 245 10 - TITLE STATEMENT |
|---|
| Title |
VLSI circuit design methodology demystified : |
| Remainder of title |
a conceptual taxonomy / |
| Statement of responsibility, etc. |
Liming Xiu. |
| 260 ## - PUBLICATION, DISTRIBUTION, ETC. |
|---|
| Place of publication, distribution, etc. |
Hoboken, N.J. : |
| Name of publisher, distributor, etc. |
Wiley ; |
| Place of publication, distribution, etc. |
[Chichester : |
| Name of publisher, distributor, etc. |
John Wiley, distributor], |
| Date of publication, distribution, etc. |
c2008. |
| 300 ## - PHYSICAL DESCRIPTION |
|---|
| Extent |
xvii, 202 p. : |
| Other physical details |
ill. ; |
| Dimensions |
24 cm. |
| 504 ## - BIBLIOGRAPHY, ETC. NOTE |
|---|
| Bibliography, etc. note |
Includes bibliographical references and index. |
| 520 ## - SUMMARY, ETC. |
|---|
| Summary, etc. |
This book was written to arm engineers qualified and knowledgeable in the area of VLSI circuits with the essential knowledge they need to get into this exciting field and to help those already in it achieve a higher level of proficiency. |
| Expansion of summary note |
This book was written to arm engineers qualified and knowledgeable in the area of VLSI circuits with the essential knowledge they need to get into this exciting field and to help those already in it achieve a higher level of proficiency. Few people truly understand how a large chip is developed, but an understanding of the whole process is necessary to appreciate the importance of each part of it and to understand the process from concept to silicon. It will teach readers how to become better engineers through a practical approach of diagnosing and attacking real-world problems. |
| 505 00 - FORMATTED CONTENTS NOTE |
|---|
| Miscellaneous information |
Chapter 1 |
| Title |
The Big Picture |
| Miscellaneous information |
1 -- |
| -- |
1 |
| Title |
What is a chip? |
| Miscellaneous information |
1 -- |
| -- |
2 |
| Title |
What are the requirements of a successful chip design? |
| Miscellaneous information |
3 -- |
| -- |
3 |
| Title |
What are the challenges in today's very deep submicron (VDSM), multimillion gate designs? |
| Miscellaneous information |
4 -- |
| -- |
4 |
| Title |
What major process technologies are used in today's design environment? |
| Miscellaneous information |
5 -- |
| -- |
5 |
| Title |
What are the goals of new chip design? |
| Miscellaneous information |
8 -- |
| -- |
6 |
| Title |
What are the major approaches of today's very large scale integration (VLSI) circuit design practices? |
| Miscellaneous information |
9 -- |
| -- |
7 |
| Title |
What is standard cell-based, application-specific integrated circuit (ASIC) design methodology? |
| Miscellaneous information |
11 -- |
| -- |
8 |
| Title |
What is the system-on-chip (SoC) approach? |
| Miscellaneous information |
12 -- |
| -- |
9 |
| Title |
What are the driving forces behind the SoC trend? |
| Miscellaneous information |
15 -- |
| -- |
10 |
| Title |
What are the major tasks in developing a SoC chip from concept to silicon? |
| Miscellaneous information |
15 -- |
| -- |
11 |
| Title |
What are the major costs of developing a chip? |
| Miscellaneous information |
16 -- |
| -- |
Chapter 2 |
| Title |
The Basics of the CMOS Process and Devices |
| Miscellaneous information |
17 -- |
| -- |
12 |
| Title |
What are the major process steps in building MOSFET transistors? |
| Miscellaneous information |
17 -- |
| -- |
13 |
| Title |
What are the two types of MOSFET transistors? |
| Miscellaneous information |
19 -- |
| -- |
14 |
| Title |
What are base layers and metal layers? |
| Miscellaneous information |
20 -- |
| -- |
15 |
| Title |
What are wafers and dies? |
| Miscellaneous information |
24 -- |
| -- |
16 |
| Title |
What is semiconductor lithography? |
| Miscellaneous information |
28 -- |
| -- |
17 |
| Title |
What is a package? |
| Miscellaneous information |
33 -- |
| -- |
Chapter 3 |
| Title |
The Challenges in VLSI Circuit Design |
| Miscellaneous information |
41 -- |
| -- |
18 |
| Title |
What is the role of functional verification in the IC design process? |
| Miscellaneous information |
41 -- |
| -- |
19 |
| Title |
What are some of the design integrity issues? |
| Miscellaneous information |
44 -- |
| -- |
20 |
| Title |
What is design for testability? |
| Miscellaneous information |
46 -- |
| -- |
21 |
| Title |
Why is reducing the chip's power consumption so important? |
| Miscellaneous information |
48 -- |
| -- |
22 |
| Title |
What are some of the challenges in chip packaging? |
| Miscellaneous information |
49 -- |
| -- |
23 |
| Title |
What are the advantages of design reuse? |
| Miscellaneous information |
50 -- |
| -- |
24 |
| Title |
What is hardware/software co-design? |
| Miscellaneous information |
51 -- |
| -- |
25 |
| Title |
Why is the clock so important? |
| Miscellaneous information |
54 -- |
| -- |
26 |
| Title |
What is the leakage current problem? |
| Miscellaneous information |
57 -- |
| -- |
27 |
| Title |
What is design for manufacturability? |
| Miscellaneous information |
60 -- |
| -- |
28 |
| Title |
What is chip reliability? |
| Miscellaneous information |
62 -- |
| -- |
29 |
| Title |
What is analog integration in the digital environment? |
| Miscellaneous information |
65 -- |
| -- |
30 |
| Title |
What is the role of EDA tools in IC design? |
| Miscellaneous information |
67 -- |
| -- |
31 |
| Title |
What is the role of the embedded processor in the SoC environment? |
| Miscellaneous information |
69 -- |
| -- |
Chapter 4 |
| Title |
Cell-Based ASIC Design Methodology |
| Miscellaneous information |
73 -- |
| -- |
32 |
| Title |
What are the major tasks and personnel required in a chip design project? |
| Miscellaneous information |
73 -- |
| -- |
33 |
| Title |
What are the major steps in ASIC chip construction? |
| Miscellaneous information |
74 -- |
| -- |
34 |
| Title |
What is the ASIC design flow? |
| Miscellaneous information |
75 -- |
| -- |
35 |
| Title |
What are the two major aspects of ASIC design flow? |
| Miscellaneous information |
77 -- |
| -- |
36 |
| Title |
What are the characteristics of good design flow? |
| Miscellaneous information |
80 -- |
| -- |
37 |
| Title |
What is the role of market research in an ASIC project? |
| Miscellaneous information |
81 -- |
| -- |
38 |
| Title |
What is the optimal solution of an ASIC project? |
| Miscellaneous information |
82 -- |
| -- |
39 |
| Title |
What is system-level study of a project? |
| Miscellaneous information |
84 -- |
| -- |
40 |
| Title |
What are the approaches for verifying design at the system level? |
| Miscellaneous information |
85 -- |
| -- |
41 |
| Title |
What is register-transfer-level (RTL) system-level description? |
| Miscellaneous information |
86 -- |
| -- |
42 |
| Title |
What are methods of verifying design at the register-transfer-level? |
| Miscellaneous information |
87 -- |
| -- |
43 |
| Title |
What is a test bench? |
| Miscellaneous information |
88 -- |
| -- |
44 |
| Title |
What is code coverage? |
| Miscellaneous information |
89 -- |
| -- |
45 |
| Title |
What is functional coverage? |
| Miscellaneous information |
89 -- |
| -- |
46 |
| Title |
What is bug rate convergence? |
| Miscellaneous information |
90 -- |
| -- |
47 |
| Title |
What is design planning? |
| Miscellaneous information |
91 -- |
| -- |
48 |
| Title |
What are hard macro and soft macro? |
| Miscellaneous information |
92 -- |
| -- |
49 |
| Title |
What is hardware description language (HDL)? |
| Miscellaneous information |
92 -- |
| -- |
50 |
| Title |
What is register-transfer-level (RTL) description of hardware? |
| Miscellaneous information |
93 -- |
| -- |
51 |
| Title |
What is standard cell? What are the differences among standard cell, gate-array, and sea-of-gate approaches? |
| Miscellaneous information |
94 -- |
| -- |
52 |
| Title |
What is an ASIC library? |
| Miscellaneous information |
103 -- |
| -- |
53 |
| Title |
What is logic synthesis? |
| Miscellaneous information |
105 -- |
| -- |
54 |
| Title |
What are the optimization targets of logic synthesis? |
| Miscellaneous information |
106 -- |
| -- |
55 |
| Title |
What is schematic or netlist? |
| Miscellaneous information |
107 -- |
| -- |
56 |
| Title |
What is the gate count of a design? |
| Miscellaneous information |
111 -- |
| -- |
57 |
| Title |
What is the purpose of test insertion during logic synthesis? |
| Miscellaneous information |
111 -- |
| -- |
58 |
| Title |
What is the most commonly used model in VLSI circuit testing? |
| Miscellaneous information |
112 -- |
| -- |
59 |
| Title |
What are controllability and observability in a digital circuit? |
| Miscellaneous information |
114 -- |
| -- |
60 |
| Title |
What is a testable circuit? |
| Miscellaneous information |
115 -- |
| -- |
61 |
| Title |
What is the aim of scan insertion? |
| Miscellaneous information |
116 -- |
| -- |
62 |
| Title |
What is fault coverage? What is defect part per million (DPPM)? |
| Miscellaneous information |
117 -- |
| -- |
63 |
| Title |
Why is design for testability important for a product's financial success? |
| Miscellaneous information |
119 -- |
| -- |
64 |
| Title |
What is chip power usage analysis? |
| Miscellaneous information |
120 -- |
| -- |
65 |
| Title |
What are the major components of CMOS power consumption? |
| Miscellaneous information |
121 -- |
| -- |
66 |
| Title |
What is power optimization? |
| Miscellaneous information |
123 -- |
| -- |
67 |
| Title |
What is VLSI physical design? |
| Miscellaneous information |
123 -- |
| -- |
68 |
| Title |
What are the problems that make VLSI physical design so challenging? |
| Miscellaneous information |
124 -- |
| -- |
69 |
| Title |
What is floorplanning? |
| Miscellaneous information |
128 -- |
| -- |
70 |
| Title |
What is the placement process? |
| Miscellaneous information |
131 -- |
| -- |
71 |
| Title |
What is the routing process? |
| Miscellaneous information |
133 -- |
| -- |
72 |
| Title |
What is a power network? |
| Miscellaneous information |
135 -- |
| -- |
73 |
| Title |
What is clock distribution? |
| Miscellaneous information |
139 -- |
| -- |
74 |
| Title |
What are the key requirements for constructing a clock tree? |
| Miscellaneous information |
143 -- |
| -- |
75 |
| Title |
What is the difference between time skew and length skew in a clock tree? |
| Miscellaneous information |
145 -- |
| -- |
76 |
| Title |
What is scan chain? |
| Miscellaneous information |
149 -- |
| -- |
77 |
| Title |
What is scan chain reordering? |
| Miscellaneous information |
151 -- |
| -- |
78 |
| Title |
What is parasitic extraction? |
| Miscellaneous information |
152 -- |
| -- |
79 |
| Title |
What is delay calculation? |
| Miscellaneous information |
155 -- |
| -- |
80 |
| Title |
What is back annotation? |
| Miscellaneous information |
156 -- |
| -- |
81 |
| Title |
What kind of signal integrity problems do place and route tools handle? |
| Miscellaneous information |
156 -- |
| -- |
82 |
| Title |
What is cross-talk delay? |
| Miscellaneous information |
157 -- |
| -- |
83 |
| Title |
What is cross-talk noise? |
| Miscellaneous information |
158 -- |
| -- |
84 |
| Title |
What is IR drop? |
| Miscellaneous information |
159 -- |
| -- |
85 |
| Title |
What are the major netlist formats for design representation? |
| Miscellaneous information |
162 -- |
| -- |
86 |
| Title |
What is gate-level logic verification before tapeout? |
| Miscellaneous information |
162 -- |
| -- |
87 |
| Title |
What is equivalence check? |
| Miscellaneous information |
163 -- |
| -- |
88 |
| Title |
What is timing verification? |
| Miscellaneous information |
164 -- |
| -- |
89 |
| Title |
What is design constraint? |
| Miscellaneous information |
165 -- |
| -- |
90 |
| Title |
What is static timing analysis (STA)? |
| Miscellaneous information |
165 -- |
| -- |
91 |
| Title |
What is simulation approach on timing verification |
| Miscellaneous information |
169 -- |
| -- |
92 |
| Title |
What is the logical-effort-based timing closure approach? |
| Miscellaneous information |
173 -- |
| -- |
93 |
| Title |
What is physical verification? |
| Miscellaneous information |
178 -- |
| -- |
94 |
| Title |
What are design rule check (DRC), design verification (DV), and geometry verification (GV)? |
| Miscellaneous information |
179 -- |
| -- |
95 |
| Title |
What is schematic verification (SV) or layout versus schematic (LVS)? |
| Miscellaneous information |
181 -- |
| -- |
96 |
| Title |
What is automatic test pattern generation (ATPG)? |
| Miscellaneous information |
182 -- |
| -- |
97 |
| Title |
What is tapeout? |
| Miscellaneous information |
184 -- |
| -- |
98 |
| Title |
What is yield? |
| Miscellaneous information |
184 -- |
| -- |
99 |
| Title |
What are the qualities of a good IC implementation designed? |
| Miscellaneous information |
187. |
| 596 ## - |
|---|
| -- |
1 |
| 650 #0 - SUBJECT ADDED ENTRY--TOPICAL TERM |
|---|
| Topical term or geographic name entry element |
Integrated circuits |
| General subdivision |
Very large scale integration. |
| 650 #0 - SUBJECT ADDED ENTRY--TOPICAL TERM |
|---|
| Topical term or geographic name entry element |
Integrated circuits |
| General subdivision |
Design. |
| 942 ## - ADDED ENTRY ELEMENTS (KOHA) |
|---|
| Koha item type |
Books |
| 994 ## - |
|---|
| -- |
Z0 |
| -- |
SUPMU |