| 000 -LEADER |
|---|
| fixed length control field |
12056cam a2200373Ia 4500 |
| 001 - CONTROL NUMBER |
|---|
| control field |
u8393 |
| 003 - CONTROL NUMBER IDENTIFIER |
|---|
| control field |
SA-PMU |
| 005 - DATE AND TIME OF LATEST TRANSACTION |
|---|
| control field |
20210418123156.0 |
| 008 - FIXED-LENGTH DATA ELEMENTS--GENERAL INFORMATION |
|---|
| fixed length control field |
050628s2005 ne a b 001 0 eng d |
| 010 ## - LIBRARY OF CONGRESS CONTROL NUMBER |
|---|
| LC control number |
2005299338 |
| 040 ## - CATALOGING SOURCE |
|---|
| Original cataloging agency |
PIT |
| Language of cataloging |
eng |
| Transcribing agency |
PIT |
| Modifying agency |
OCLCQ |
| -- |
DLC |
| -- |
BAKER |
| -- |
LVB |
| -- |
YDXCP |
| -- |
BTCTA |
| -- |
NLGGC |
| -- |
OCLCG |
| -- |
BDX |
| -- |
HDC |
| -- |
SGB |
| -- |
OCLCF |
| 020 ## - INTERNATIONAL STANDARD BOOK NUMBER |
|---|
| International Standard Book Number |
0127518037 |
| 020 ## - INTERNATIONAL STANDARD BOOK NUMBER |
|---|
| International Standard Book Number |
9780127518039 |
| 035 ## - SYSTEM CONTROL NUMBER |
|---|
| System control number |
(OCoLC)60756339 |
| 050 00 - LIBRARY OF CONGRESS CALL NUMBER |
|---|
| Classification number |
TK7874.58 |
| Item number |
.W55 2005 |
| 082 00 - DEWEY DECIMAL CLASSIFICATION NUMBER |
|---|
| Classification number |
621.3815/48 |
| Edition number |
22 |
| 100 1# - MAIN ENTRY--PERSONAL NAME |
|---|
| Personal name |
Wile, Bruce. |
| 245 10 - TITLE STATEMENT |
|---|
| Title |
Comprehensive functional verification the complete industry cycle / |
| Statement of responsibility, etc. |
Bruce Wile, John C. Goss, Wolfgang Roesner. |
| 260 ## - PUBLICATION, DISTRIBUTION, ETC. |
|---|
| Place of publication, distribution, etc. |
Amsterdam ; |
| -- |
Boston : |
| Name of publisher, distributor, etc. |
Elsevier/Morgan Kaufmann, |
| Date of publication, distribution, etc. |
c2005. |
| 300 ## - PHYSICAL DESCRIPTION |
|---|
| Extent |
xiii, 676 p. : |
| Other physical details |
ill. ; |
| Dimensions |
24 cm. |
| 504 ## - BIBLIOGRAPHY, ETC. NOTE |
|---|
| Bibliography, etc. note |
Includes bibliographical references (p. 657-662) and index. |
| 505 00 - FORMATTED CONTENTS NOTE |
|---|
| Miscellaneous information |
Part I |
| Title |
Introduction to Verification -- |
| Miscellaneous information |
1 |
| Title |
Verification in the Chip Design Process |
| Miscellaneous information |
5 -- |
| -- |
1.1 |
| Title |
Introduction to Functional Verification |
| Miscellaneous information |
5 -- |
| -- |
1.2 |
| Title |
The Verification Challenge |
| Miscellaneous information |
8 -- |
| -- |
1.2.1 |
| Title |
The Challenge of State Space Explosion |
| Miscellaneous information |
9 -- |
| -- |
1.2.2 |
| Title |
The Challenge of Detecting Incorrect Behavior |
| Miscellaneous information |
12 -- |
| -- |
1.3 |
| Title |
Mission and Goals of Verification |
| Miscellaneous information |
14 -- |
| -- |
1.3.1 |
| Title |
Verification Engineer "Musts" |
| Miscellaneous information |
18 -- |
| -- |
1.4 |
| Title |
Cost of Verification |
| Miscellaneous information |
20 -- |
| -- |
1.4.1 |
| Title |
Engineering Costs and the Need for an Independent Verification Team |
| Miscellaneous information |
20 -- |
| -- |
1.4.2 |
| Title |
Design Automation Tools |
| Miscellaneous information |
21 -- |
| -- |
1.4.3 |
| Title |
Time |
| Miscellaneous information |
22 -- |
| -- |
1.5 |
| Title |
Areas of Verification Beyond the Scope of this Book |
| Miscellaneous information |
23 -- |
| -- |
1.6 |
| Title |
The Verification Cycle: A Structured Process |
| Miscellaneous information |
24 -- |
| -- |
1.6.1 |
| Title |
Functional Specification |
| Miscellaneous information |
25 -- |
| -- |
1.6.2 |
| Title |
Create Verification Plan |
| Miscellaneous information |
26 -- |
| -- |
1.6.3 |
| Title |
Develop Environment |
| Miscellaneous information |
27 -- |
| -- |
1.6.4 |
| Title |
Debug HDL and Environment |
| Miscellaneous information |
27 -- |
| -- |
1.6.5 |
| Title |
Regression |
| Miscellaneous information |
28 -- |
| -- |
1.6.6 |
| Title |
Fabricate Hardware |
| Miscellaneous information |
28 -- |
| -- |
1.6.7 |
| Title |
Debug Fabricated Hardware (Systems Test) |
| Miscellaneous information |
29 -- |
| -- |
1.6.8 |
| Title |
Escape Analysis |
| Miscellaneous information |
29 -- |
| -- |
1.6.9 |
| Title |
Common Verification Cycle Breakdowns |
| Miscellaneous information |
30 -- |
| -- |
2 |
| Title |
Verification Flow |
| Miscellaneous information |
35 -- |
| -- |
2.1 |
| Title |
Verification Hierarchy |
| Miscellaneous information |
35 -- |
| -- |
2.1.1 |
| Title |
Levels of Verification |
| Miscellaneous information |
36 -- |
| -- |
2.1.2 |
| Title |
What Level to Choose? |
| Miscellaneous information |
41 -- |
| -- |
2.2 |
| Title |
Strategy of Verification |
| Miscellaneous information |
45 -- |
| -- |
2.2.1 |
| Title |
Driving Principles |
| Miscellaneous information |
45 -- |
| -- |
2.2.2 |
| Title |
Checking Strategies |
| Miscellaneous information |
50 -- |
| -- |
2.2.3 |
| Title |
Checking the Black Box |
| Miscellaneous information |
55 -- |
| -- |
2.2.5 |
| Title |
The General Simulation Environment |
| Miscellaneous information |
61 -- |
| -- |
2.2.6 |
| Title |
Verification Methodology Evolution |
| Miscellaneous information |
62 -- |
| -- |
3 |
| Title |
Fundamentals of Simulation Based Verification |
| Miscellaneous information |
73 -- |
| -- |
3.1 |
| Title |
Basic Verification Environment: A Test Bench |
| Miscellaneous information |
73 -- |
| -- |
3.1.1 |
| Title |
Stimulus Component |
| Miscellaneous information |
74 -- |
| -- |
3.1.2 |
| Title |
Monitor |
| Miscellaneous information |
80 -- |
| -- |
3.1.3 |
| Title |
Checker |
| Miscellaneous information |
82 -- |
| -- |
3.1.4 |
| Title |
Scoreboard |
| Miscellaneous information |
83 -- |
| -- |
3.1.5 |
| Title |
Design Under Verification |
| Miscellaneous information |
85 -- |
| -- |
3.2 |
| Title |
Observation Points: Black-Box, White-Box and Grey-Box Verification |
| Miscellaneous information |
86 -- |
| -- |
3.2.1 |
| Title |
Black Box |
| Miscellaneous information |
86 -- |
| -- |
3.2.2 |
| Title |
White Box |
| Miscellaneous information |
87 -- |
| -- |
3.2.3 |
| Title |
Grey Box |
| Miscellaneous information |
88 -- |
| -- |
3.3 |
| Title |
Assertion Based Verification-An Overview |
| Miscellaneous information |
89 -- |
| -- |
3.3.1 |
| Title |
The Importance of Assertions |
| Miscellaneous information |
90 -- |
| -- |
3.3.2 |
| Title |
Assertions Express Design Intent |
| Miscellaneous information |
92 -- |
| -- |
3.3.3 |
| Title |
Classification of Assertions |
| Miscellaneous information |
94 -- |
| -- |
3.4 |
| Title |
Test Benches and Testing Strategies |
| Miscellaneous information |
95 -- |
| -- |
3.4.1 |
| Title |
Deterministic Test Benches |
| Miscellaneous information |
95 -- |
| -- |
3.4.2 |
| Title |
Self-Checking Test Benches |
| Miscellaneous information |
97 -- |
| -- |
4 |
| Title |
The Verification Plan |
| Miscellaneous information |
103 -- |
| -- |
4.1 |
| Title |
The Functional Specification |
| Miscellaneous information |
103 -- |
| -- |
4.2 |
| Title |
The Evolution of the Verification Plan |
| Miscellaneous information |
104 -- |
| -- |
4.3 |
| Title |
Contents of the Verification Plan |
| Miscellaneous information |
106 -- |
| -- |
4.3.1 |
| Title |
Description of Verification Levels |
| Miscellaneous information |
106 -- |
| -- |
4.3.2 |
| Title |
Required Tools |
| Miscellaneous information |
107 -- |
| -- |
4.3.3 |
| Title |
Risks and Dependencies |
| Miscellaneous information |
108 -- |
| -- |
4.3.4 |
| Title |
Functions to be Verified |
| Miscellaneous information |
109 -- |
| -- |
4.3.5 |
| Title |
Specific Tests and Methods: Environment |
| Miscellaneous information |
111 -- |
| -- |
4.3.6 |
| Title |
Coverage Requirements |
| Miscellaneous information |
115 -- |
| -- |
4.3.7 |
| Title |
Test Case Scenarios: Matrix |
| Miscellaneous information |
116 -- |
| -- |
4.3.8 |
| Title |
Resource Requirements |
| Miscellaneous information |
117 -- |
| -- |
4.3.9 |
| Title |
Schedule Details |
| Miscellaneous information |
118 -- |
| -- |
4.4 |
| Title |
Verification Example: Calc1 |
| Miscellaneous information |
121 -- |
| -- |
4.4.1 |
| Title |
Design Description |
| Miscellaneous information |
121 -- |
| -- |
4.4.2 |
| Title |
Creating the Verification Plan for Calc1 |
| Miscellaneous information |
125 -- |
| -- |
4.4.3 |
| Title |
Deterministic Verification of Calc1 |
| Miscellaneous information |
131 -- |
| -- |
Part II |
| Title |
Simulation Based Verification -- |
| Miscellaneous information |
5 |
| Title |
HDLs and Simulation Engines |
| Miscellaneous information |
141 -- |
| -- |
5.1 |
| Title |
Hardware Description Languages |
| Miscellaneous information |
143 -- |
| -- |
5.1.1 |
| Title |
HDL Modeling Levels |
| Miscellaneous information |
143 -- |
| -- |
5.1.2 |
| Title |
Verification Aspects of HDLs |
| Miscellaneous information |
153 -- |
| -- |
5.2 |
| Title |
Simulation Engines: Introduction |
| Miscellaneous information |
159 -- |
| -- |
5.2.1 |
| Title |
Speed versus Accuracy |
| Miscellaneous information |
160 -- |
| -- |
5.2.2 |
| Title |
Making the Right Methodology Choices |
| Miscellaneous information |
162 -- |
| -- |
5.3 |
| Title |
Event-Driven Simulation |
| Miscellaneous information |
162 -- |
| -- |
5.3.1 |
| Title |
Hierarchical Model Network |
| Miscellaneous information |
163 -- |
| -- |
5.3.2 |
| Title |
Model Evaluation Over Time |
| Miscellaneous information |
165 -- |
| -- |
5.3.3 |
| Title |
Event-Driven Control of Model Evaluation |
| Miscellaneous information |
167 -- |
| -- |
5.3.4 |
| Title |
Implementation Sketch of an Event-Driven Simulation Engine |
| Miscellaneous information |
172 -- |
| -- |
5.4 |
| Title |
Improving Simulation Throughput |
| Miscellaneous information |
178 -- |
| -- |
5.5 |
| Title |
Cycle-Based Simulation |
| Miscellaneous information |
182 -- |
| -- |
5.5.1 |
| Title |
Synchronous Design |
| Miscellaneous information |
183 -- |
| -- |
5.5.2 |
| Title |
The Cycle-Based Simulation Algorithm |
| Miscellaneous information |
184 -- |
| -- |
5.5.3 |
| Title |
Extensions to Basic Cycle-Based Simulation Engines |
| Miscellaneous information |
188 -- |
| -- |
5.6 |
| Title |
Waveform Viewers |
| Miscellaneous information |
191 -- |
| -- |
6 |
| Title |
Creating Environments |
| Miscellaneous information |
199 -- |
| -- |
6.1 |
| Title |
Test Bench Writing Tools |
| Miscellaneous information |
200 -- |
| -- |
6.1.1 |
| Title |
HDL Languages as Test Bench Tool |
| Miscellaneous information |
201 -- |
| -- |
6.1.2 |
| Title |
C/C++ Libraries |
| Miscellaneous information |
207 -- |
| -- |
6.1.3 |
| Title |
High-Level Verification Languages |
| Miscellaneous information |
230 -- |
| -- |
6.1.4 |
| Title |
Other Test Bench Tools |
| Miscellaneous information |
241 -- |
| -- |
6.2 |
| Title |
Verification Coverage |
| Miscellaneous information |
243 -- |
| -- |
6.2.2 |
| Title |
Functional Verification Test Coverage versus Manufacturing Test Coverage |
| Miscellaneous information |
246 -- |
| -- |
6.2.3 |
| Title |
Structural Coverage |
| Miscellaneous information |
247 -- |
| -- |
6.2.4 |
| Title |
Functional Coverage |
| Miscellaneous information |
251 -- |
| -- |
6.2.5 |
| Title |
Coverage Bulk Data Collection and Management |
| Miscellaneous information |
254 -- |
| -- |
6.2.6 |
| Title |
The Right Coverage Analysis Strategy |
| Miscellaneous information |
255 -- |
| -- |
7 |
| Title |
Strategies for Simulation-Based Stimulus Generation |
| Miscellaneous information |
259 -- |
| -- |
7.1 |
| Title |
Calc2 Overview |
| Miscellaneous information |
260 -- |
| -- |
7.1.1 |
| Title |
Calc2 Verification Plan |
| Miscellaneous information |
263 -- |
| -- |
7.1.2 |
| Title |
Calc2 and the Strategies for Stimulus Generation |
| Miscellaneous information |
269 -- |
| -- |
7.2 |
| Title |
Strategies for Stimulus Generation |
| Miscellaneous information |
270 -- |
| -- |
7.2.1 |
| Title |
Types of Stimulus Generation |
| Miscellaneous information |
270 -- |
| -- |
7.2.2 |
| Title |
General Algorithms for Stimulus Components |
| Miscellaneous information |
275 -- |
| -- |
7.2.3 |
| Title |
Applying the Four Types of Stimulus Generation to Calc2 |
| Miscellaneous information |
277 -- |
| -- |
7.2.4 |
| Title |
Seeding Random Test Cases |
| Miscellaneous information |
294 -- |
| -- |
7.2.5 |
| Title |
Constraint Solving in Random Environments |
| Miscellaneous information |
297 -- |
| -- |
7.2.6 |
| Title |
Coverage Techniques in Random Environments |
| Miscellaneous information |
301 -- |
| -- |
7.2.7 |
| Title |
Making Rare Events Occur |
| Miscellaneous information |
303 -- |
| -- |
7.2.8 |
| Title |
Stimulus Generation of Deadlocks and Livelocks |
| Miscellaneous information |
306 -- |
| -- |
8 |
| Title |
Strategies for Results Checking in Simulation-Based Verification |
| Miscellaneous information |
313 -- |
| -- |
8.1 |
| Title |
Types of Result Checking |
| Miscellaneous information |
313 -- |
| -- |
8.1.1 |
| Title |
On-the-Fly Checking versus End-of-Test Case Checking |
| Miscellaneous information |
314 -- |
| -- |
8.1.2 |
| Title |
Pregenerated Test Cases versus On-the-Fly Generated Test Cases |
| Miscellaneous information |
321 -- |
| -- |
8.1.3 |
| Title |
Applying the Checking Strategies to Calc2 |
| Miscellaneous information |
322 -- |
| -- |
8.2 |
| Title |
Debug |
| Miscellaneous information |
334 -- |
| -- |
8.2.1 |
| Title |
Debug Process |
| Miscellaneous information |
336 -- |
| -- |
8.2.2 |
| Title |
How Different Types of Test Benches Affect Debug |
| Miscellaneous information |
349 -- |
| -- |
9 |
| Title |
Pervasive Function Verification |
| Miscellaneous information |
355 -- |
| -- |
9.1 |
| Title |
System Reset and Bring-Up |
| Miscellaneous information |
356 -- |
| -- |
9.1.1 |
| Title |
Reset Line Initialization |
| Miscellaneous information |
357 -- |
| -- |
9.1.2 |
| Title |
Scan Initialization |
| Miscellaneous information |
361 -- |
| -- |
9.1.3 |
| Title |
Testability and Built-In Self-Test |
| Miscellaneous information |
363 -- |
| -- |
9.2 |
| Title |
Error and Degraded Mode Handling |
| Miscellaneous information |
368 -- |
| -- |
9.2.1 |
| Title |
Verifying Error Detection |
| Miscellaneous information |
368 -- |
| -- |
9.2.2 |
| Title |
Verifying Self-Healing Hardware |
| Miscellaneous information |
372 -- |
| -- |
9.3 |
| Title |
Verifying Hardware Debug Assists |
| Miscellaneous information |
380 -- |
| -- |
9.3.1 |
| Title |
Verifying Scan Ring Dumps |
| Miscellaneous information |
381 -- |
| Title |
Low Power Mode Verification |
| Miscellaneous information |
384 -- |
| -- |
9.4.1 |
| Title |
Power Savings Through Disabling Functional Units |
| Miscellaneous information |
385 -- |
| -- |
9.4.2 |
| Title |
Power Savings Through Cycle Time Degradation |
| Miscellaneous information |
387 -- |
| -- |
10 |
| Title |
Re-Use Strategies and System Simulation |
| Miscellaneous information |
391 -- |
| -- |
10.1 |
| Title |
Re-Use Strategies |
| Miscellaneous information |
392 -- |
| -- |
10.1.1 |
| Title |
Guidelines for Re-Use |
| Miscellaneous information |
395 -- |
| -- |
10.1.2 |
| Title |
Horizontal Re-Use |
| Miscellaneous information |
403 -- |
| -- |
10.1.3 |
| Title |
Vertical Re-Use |
| Miscellaneous information |
404 -- |
| -- |
10.1.4 |
| Title |
Applying Re-Use to Calc2 |
| Miscellaneous information |
405 -- |
| -- |
10.1.5 |
| Title |
Assertion Re-Use |
| Miscellaneous information |
410 -- |
| -- |
10.2 |
| Title |
System Simulation |
| Miscellaneous information |
412 -- |
| -- |
10.2.1 |
| Title |
System Test Bench |
| Miscellaneous information |
412 -- |
| -- |
10.2.2 |
| Title |
Connectivity and Interaction of Units |
| Miscellaneous information |
414 -- |
| -- |
10.2.3 |
| Title |
Verification Challenges in a Re-Usable IP World |
| Miscellaneous information |
418 -- |
| -- |
10.3 |
| Title |
Beyond General-Purpose Logic Simulation |
| Miscellaneous information |
420 -- |
| -- |
10.3.1 |
| Title |
Acceleration |
| Miscellaneous information |
421 -- |
| -- |
10.3.2 |
| Title |
Emulation |
| Miscellaneous information |
427 -- |
| -- |
10.3.3 |
| Title |
Hardware/Software Co-verification |
| Miscellaneous information |
428 -- |
| -- |
10.3.4 |
| Title |
Co-simulation |
| Miscellaneous information |
430 -- |
| -- |
Part III |
| Title |
Formal Verification -- |
| Miscellaneous information |
11 |
| Title |
Introduction to Formal Verification |
| Miscellaneous information |
439 -- |
| -- |
11.1.1 |
| Title |
Design Correctness and Specifications |
| Miscellaneous information |
441 -- |
| -- |
11.1.2 |
| Title |
Computational Complexity |
| Miscellaneous information |
443 -- |
| -- |
11.1.3 |
| Title |
The Myth of Linear Scaling of Simulation |
| Miscellaneous information |
445 -- |
| -- |
11.1.4 |
| Title |
Mathematical Proof Methods in Formal Verification |
| Miscellaneous information |
446 -- |
| -- |
11.2 |
| Title |
Formal Boolean Equivalence Checking |
| Miscellaneous information |
448 -- |
| -- |
11.2.1 |
| Title |
The Role of Equivalence Checking in the VLSI Design Flow |
| Miscellaneous information |
449 -- |
| -- |
11.2.2 |
| Title |
Main Elements of an Equivalence Checker Tool |
| Miscellaneous information |
450 -- |
| -- |
11.2.3 |
| Title |
Sequential and Combinational Boolean Equivalence Checking |
| Miscellaneous information |
451 -- |
| -- |
11.2.4 |
| Title |
Core Algorithms for Combinational Equivalence Checking |
| Miscellaneous information |
454 -- |
| -- |
11.2.5 |
| Title |
Blueprint of a Modern Equivalence Checking Tool |
| Miscellaneous information |
465 -- |
| -- |
11.3 |
| Title |
Functional Formal Verification-Property Checking |
| Miscellaneous information |
467 -- |
| -- |
11.3.1 |
| Title |
Property Checking vs. |
| 505 00 - FORMATTED CONTENTS NOTE |
|---|
| Title |
Sequential Equivalence Checking |
| Miscellaneous information |
468 -- |
| -- |
11.3.2 |
| Title |
The Myth of Complete Verification with FV |
| Miscellaneous information |
470 -- |
| -- |
11.3.3 |
| Title |
Properties for an Example Design |
| Miscellaneous information |
471 -- |
| -- |
11.3.4 |
| Title |
DUV Drivers for Formal Verification |
| Miscellaneous information |
476 -- |
| -- |
11.3.5 |
| Title |
State Space Traversal and Temporal Logic |
| Miscellaneous information |
479 -- |
| -- |
11.3.6 |
| Title |
Functional Formal Verification Tool Flow |
| Miscellaneous information |
483 -- |
| -- |
12 |
| Title |
Using Formal Verification |
| Miscellaneous information |
487 -- |
| -- |
12.1 |
| Title |
Property Specification Using an HDL Library |
| Miscellaneous information |
488 -- |
| -- |
12.1.1 |
| Title |
The Open Verification Library (OVL) |
| Miscellaneous information |
489 -- |
| -- |
12.1.2 |
| Title |
Using OVL to Specify Properties |
| Miscellaneous information |
495 -- |
| -- |
12.2 |
| Title |
The Property Specification Language PSL |
| Miscellaneous information |
499 -- |
| -- |
12.2.2 |
| Title |
The Boolean Layer of PSL |
| Miscellaneous information |
501 -- |
| -- |
12.2.3 |
| Title |
The Temporal Layer of PSL |
| Miscellaneous information |
504 -- |
| -- |
12.2.4 |
| Title |
The Verification Layer of PSL |
| Miscellaneous information |
508 -- |
| -- |
12.2.5 |
| Title |
The Modeling Layer of PSL |
| Miscellaneous information |
511 -- |
| -- |
12.2.6 |
| Title |
Using PSL to Specify Properties |
| Miscellaneous information |
512 -- |
| -- |
12.2.7 |
| Title |
Advanced PSL Topics and Caveats |
| Miscellaneous information |
514 -- |
| -- |
12.3 |
| Title |
Property Checking Using Formal Verification |
| Miscellaneous information |
521 -- |
| -- |
12.3.1 |
| Title |
Property Re-Use between Simulation and FV |
| Miscellaneous information |
521 -- |
| -- |
12.3.2 |
| Title |
Model Compliation |
| Miscellaneous information |
522 -- |
| -- |
12.3.3 |
| Title |
Formal Functional Verification Algorithms |
| Miscellaneous information |
523 -- |
| -- |
12.3.4 |
| Title |
Solutions to Address the Problem of State Space Explosion |
| Miscellaneous information |
527 -- |
| -- |
12.3.5 |
| Title |
Semi-Formal Verification |
| Miscellaneous information |
530 -- |
| -- |
12.3.6 |
| Title |
EDA Vendors Supplying Formal and Semi-Formal Verification Tools |
| Miscellaneous information |
532 -- |
| -- |
Part IV |
| Title |
Comprehensive Verification -- |
| Miscellaneous information |
13 |
| Title |
Completing the Verification Cycle |
| Miscellaneous information |
539 -- |
| -- |
13.1 |
| Title |
Regression |
| Miscellaneous information |
540 -- |
| -- |
13.1.1 |
| Title |
Regression in the Verification Flow |
| Miscellaneous information |
540 -- |
| -- |
13.1.2 |
| Title |
Regression Quality |
| Miscellaneous information |
542 -- |
| -- |
13.1.3 |
| Title |
Regression Efficiency |
| Miscellaneous information |
543 -- |
| -- |
13.2 |
| Title |
Problem Tracking |
| Miscellaneous information |
548 -- |
| -- |
13.3 |
| Title |
Tape-Out Readiness |
| Miscellaneous information |
552 -- |
| -- |
13.3.1 |
| Title |
Metrics |
| Miscellaneous information |
552 -- |
| -- |
13.3.2 |
| Title |
Completion Criteria |
| Miscellaneous information |
557 -- |
| -- |
13.4 |
| Title |
Escape Analysis |
| Miscellaneous information |
559 -- |
| -- |
13.4.1 |
| Title |
Individual Bug Analysis |
| Miscellaneous information |
561 -- |
| -- |
13.4.2 |
| Title |
Escape Examples |
| Miscellaneous information |
569 -- |
| -- |
13.4.3 |
| Title |
Escape Analysis Trends |
| Miscellaneous information |
572 -- |
| -- |
14 |
| Title |
Advanced Verification Techniques |
| Miscellaneous information |
579 -- |
| -- |
14.1 |
| Title |
Save Verification Cycles-Bootstrapping the Verification Process |
| Miscellaneous information |
580 -- |
| -- |
14.1.1 |
| Title |
Separating POR and Mainline Verification |
| Miscellaneous information |
580 -- |
| -- |
14.1.2 |
| Title |
Bootstrapping the DUV into High-Potential States |
| Miscellaneous information |
583 -- |
| -- |
14.1.3 |
| Title |
Manipulating the DUV Specification Provoking States of Resource Conflict |
| Miscellaneous information |
585 -- |
| -- |
14.2 |
| Title |
High-Level Modeling-Concepts |
| Miscellaneous information |
586 -- |
| -- |
14.2.1 |
| Title |
Applications of the High-Level Model |
| Miscellaneous information |
587 -- |
| -- |
14.2.2 |
| Title |
High-Level Modeling Styles |
| Miscellaneous information |
590 -- |
| -- |
14.3 |
| Title |
Coverage-Directed Generation |
| Miscellaneous information |
595 -- |
| -- |
15.1 |
| Title |
The Line Delete Escape |
| Miscellaneous information |
603 -- |
| -- |
15.1.1 |
| Title |
The Background |
| Miscellaneous information |
603 -- |
| -- |
15.1.2 |
| Title |
The Verification Environments |
| Miscellaneous information |
605 -- |
| -- |
15.1.3 |
| Title |
The Escape |
| Miscellaneous information |
607 -- |
| -- |
15.2 |
| Title |
Branch History Table |
| Miscellaneous information |
608 |
| 520 ## - SUMMARY, ETC. |
|---|
| Summary, etc. |
A key strength of this book is that it describes the entire verification cycle and details each stage. The organization of the book follows the cycle, demonstrating how functional verification engages all aspects of the overall design effort and how individual cycle stages relate to the larger design process. Throughout the text, the authors leverage their 35 plus years experience in functional verification, providing examples and case studies, and focusing on the skills, methods, and tools needed to complete each verification task. Additionally, the major vendors (Mentor Graphics, Cadence Design Systems, Verisity, and Synopsys) have implemented key examples from the text and made these available on line, so that the reader can test out the methods described in the text. |
| 596 ## - |
|---|
| -- |
1 2 |
| 650 #0 - SUBJECT ADDED ENTRY--TOPICAL TERM |
|---|
| Topical term or geographic name entry element |
Integrated circuits |
| General subdivision |
Verification. |
| 650 #0 - SUBJECT ADDED ENTRY--TOPICAL TERM |
|---|
| Topical term or geographic name entry element |
Computer engineering. |
| 700 1# - ADDED ENTRY--PERSONAL NAME |
|---|
| Personal name |
Goss, John C. |
| 700 1# - ADDED ENTRY--PERSONAL NAME |
|---|
| Personal name |
Roesner, W. |
| Fuller form of name |
(Wolfgang) |
| 856 42 - ELECTRONIC LOCATION AND ACCESS |
|---|
| Materials specified |
Publisher description |
| Uniform Resource Identifier |
<a href="http://catdir.loc.gov/catdir/enhancements/fy0627/2005299338-d.html">http://catdir.loc.gov/catdir/enhancements/fy0627/2005299338-d.html</a> |
| 856 41 - ELECTRONIC LOCATION AND ACCESS |
|---|
| Materials specified |
Table of contents |
| Uniform Resource Identifier |
<a href="http://catdir.loc.gov/catdir/enhancements/fy0627/2005299338-t.html">http://catdir.loc.gov/catdir/enhancements/fy0627/2005299338-t.html</a> |
| 942 ## - ADDED ENTRY ELEMENTS (KOHA) |
|---|
| Koha item type |
Books |
| 994 ## - |
|---|
| -- |
Z0 |
| -- |
SUPMU |