| 000 -LEADER |
|---|
| fixed length control field |
11372cam a22003737a 4500 |
| 001 - CONTROL NUMBER |
|---|
| control field |
u8408 |
| 003 - CONTROL NUMBER IDENTIFIER |
|---|
| control field |
SA-PMU |
| 005 - DATE AND TIME OF LATEST TRANSACTION |
|---|
| control field |
20210418123258.0 |
| 008 - FIXED-LENGTH DATA ELEMENTS--GENERAL INFORMATION |
|---|
| fixed length control field |
070419s2006 caua 001 0 eng d |
| 010 ## - LIBRARY OF CONGRESS CONTROL NUMBER |
|---|
| LC control number |
2007296561 |
| 040 ## - CATALOGING SOURCE |
|---|
| Original cataloging agency |
UIU |
| Language of cataloging |
eng |
| Transcribing agency |
UIU |
| Modifying agency |
DLC |
| -- |
YDXCP |
| -- |
BAKER |
| -- |
LML |
| -- |
BTCTA |
| -- |
AU@ |
| -- |
UKM |
| -- |
MIA |
| -- |
CUY |
| -- |
HDC |
| -- |
GPM |
| -- |
LVB |
| -- |
CUD |
| -- |
SZ9XM |
| -- |
OCLCO |
| -- |
OCLCF |
| 020 ## - INTERNATIONAL STANDARD BOOK NUMBER |
|---|
| International Standard Book Number |
0123695260 |
| 020 ## - INTERNATIONAL STANDARD BOOK NUMBER |
|---|
| International Standard Book Number |
9780123695260 |
| 035 ## - SYSTEM CONTROL NUMBER |
|---|
| System control number |
(OCoLC)72535240 |
| Canceled/invalid control number |
(OCoLC)69733202 |
| -- |
(OCoLC)84843363 |
| 042 ## - AUTHENTICATION CODE |
|---|
| Authentication code |
lccopycat |
| 050 00 - LIBRARY OF CONGRESS CALL NUMBER |
|---|
| Classification number |
TK7895.E42 |
| Item number |
C88 2007 |
| 082 04 - DEWEY DECIMAL CLASSIFICATION NUMBER |
|---|
| Classification number |
621.392 |
| Edition number |
22 |
| 245 00 - TITLE STATEMENT |
|---|
| Title |
Customizable embedded processors : |
| Remainder of title |
design technologies and applications / |
| Statement of responsibility, etc. |
Paolo Ienne and Rainer Leupers [editors]. |
| 260 ## - PUBLICATION, DISTRIBUTION, ETC. |
|---|
| Place of publication, distribution, etc. |
San Francisco, Calif. : |
| Name of publisher, distributor, etc. |
Morgan Kaufmann ; |
| Place of publication, distribution, etc. |
Oxford : |
| Name of publisher, distributor, etc. |
Elsevier Science [distributor], |
| Date of publication, distribution, etc. |
2006. |
| 300 ## - PHYSICAL DESCRIPTION |
|---|
| Extent |
xxviii, 497 p. : |
| Other physical details |
ill. ; |
| Dimensions |
25 cm. |
| 490 1# - SERIES STATEMENT |
|---|
| Series statement |
Morgan Kaufmann series in systems on silicon |
| 504 ## - BIBLIOGRAPHY, ETC. NOTE |
|---|
| Bibliography, etc. note |
Includes bibliographical references (p. [465]-484) and index. |
| 505 00 - FORMATTED CONTENTS NOTE |
|---|
| Title |
In Praise of Customizable Embedded Processors |
| Miscellaneous information |
i -- |
| -- |
Part I |
| Title |
Opportunities and Challenges -- |
| Miscellaneous information |
1 |
| Title |
From Pret-a-Porter to Tailor-Made / |
| Statement of responsibility |
Paolo Ienne, Rainer Leupers |
| Miscellaneous information |
3 -- |
| -- |
1.1 |
| Title |
The Call for Flexibility |
| Miscellaneous information |
4 -- |
| -- |
1.2 |
| Title |
Cool Chips for Shallow Pockets |
| Miscellaneous information |
5 -- |
| -- |
1.3 |
| Title |
A Million Processors for the Price of One? |
| Miscellaneous information |
5 -- |
| -- |
1.4 |
| Title |
Processors Coming of Age |
| Miscellaneous information |
7 -- |
| -- |
1.6 |
| Title |
Travel Broadens the Mind |
| Miscellaneous information |
9 -- |
| -- |
2 |
| Title |
Opportunities for Application-Specific Processors: The Case of Wireless Communications / |
| Statement of responsibility |
Gerd Ascheid, Heinrich Meyr |
| Miscellaneous information |
11 -- |
| -- |
2.1 |
| Title |
Future Mobile Communication Systems |
| Miscellaneous information |
12 -- |
| -- |
2.2 |
| Title |
Heterogeneous MPSoC for Digital Receivers |
| Miscellaneous information |
14 -- |
| -- |
2.2.1 |
| Title |
The Fundamental Tradeoff between Energy Efficiency and Flexibility |
| Miscellaneous information |
14 -- |
| -- |
2.2.2 |
| Title |
How to Exploit the Huge Design Space? |
| Miscellaneous information |
17 -- |
| -- |
2.2.3 |
| Title |
Canonical Receiver Structure |
| Miscellaneous information |
19 -- |
| -- |
2.2.4 |
| Title |
Analyzing and Classifying the Functions of a Digital Receiver |
| Miscellaneous information |
21 -- |
| -- |
2.2.5 |
| Title |
Exploiting Parallelism |
| Miscellaneous information |
25 -- |
| -- |
2.3 |
| Title |
ASIP Design |
| Miscellaneous information |
26 -- |
| -- |
2.3.1 |
| Title |
Processor Design Flow |
| Miscellaneous information |
26 -- |
| -- |
2.3.2 |
| Title |
Architecture Description Language Based Design |
| Miscellaneous information |
28 -- |
| -- |
2.3.3 |
| Title |
Too Much Automation Is Bad |
| Miscellaneous information |
29 -- |
| -- |
2.3.4 |
| Title |
Processor Design: The LISATek Approach |
| Miscellaneous information |
30 -- |
| -- |
2.3.5 |
| Title |
Design Competence Rules the World |
| Miscellaneous information |
33 -- |
| -- |
2.3.6 |
| Title |
Application-Specific or Domain-Specific Processors? |
| Miscellaneous information |
35 -- |
| -- |
3 |
| Title |
Customizing Processors: Lofty Ambitions, Stark Realities / |
| Statement of responsibility |
Joseph A. Fisher, Paolo Faraboschi, Cliff Young |
| Miscellaneous information |
39 -- |
| -- |
3.1 |
| Title |
The "CFP" project at HP Labs |
| Miscellaneous information |
41 -- |
| -- |
3.2 |
| Title |
Searching for the Best Architecture Is Not a Machine-Only Endeavor |
| Miscellaneous information |
45 -- |
| -- |
3.3 |
| Title |
Designing a CPU Core Still Takes a Very Long Time |
| Miscellaneous information |
46 -- |
| -- |
3.4 |
| Title |
Don't Underestimate Competitive Technologies |
| Miscellaneous information |
48 -- |
| -- |
3.5 |
| Title |
Software Developers Don't Always Help You |
| Miscellaneous information |
49 -- |
| -- |
3.6 |
| Title |
The Embedded World Is Not Immune to Legacy Problems |
| Miscellaneous information |
51 -- |
| -- |
3.7 |
| Title |
Customization Can Be Trouble |
| Miscellaneous information |
52 -- |
| -- |
Part II |
| Title |
Aspects of Processor Customization -- |
| Miscellaneous information |
4 |
| Title |
Architecture Description Languages / |
| Statement of responsibility |
Prabhat Mishra, Nikil Dutt |
| Miscellaneous information |
59 -- |
| -- |
4.1 |
| Title |
ADLs and other languages |
| Miscellaneous information |
60 -- |
| -- |
4.2 |
| Title |
Survey of Contemporary ADLs |
| Miscellaneous information |
62 -- |
| -- |
4.2.1 |
| Title |
Content-Oriented Classification of ADLs |
| Miscellaneous information |
62 -- |
| -- |
4.2.2 |
| Title |
Objective-Based Classification of ADLs |
| Miscellaneous information |
72 -- |
| -- |
5 |
| Title |
C Compiler Retargeting / |
| Statement of responsibility |
Rainer Leupers |
| Miscellaneous information |
77 -- |
| -- |
5.1 |
| Title |
Compiler Construction Background |
| Miscellaneous information |
79 -- |
| -- |
5.1.1 |
| Title |
Source Language Frontend |
| Miscellaneous information |
79 -- |
| -- |
5.1.2 |
| Title |
Intermediate Representation and Optimization |
| Miscellaneous information |
80 -- |
| -- |
5.1.3 |
| Title |
Machine Code Generation |
| Miscellaneous information |
83 -- |
| -- |
5.2 |
| Title |
Approaches to Retargetable Compilation |
| Miscellaneous information |
91 -- |
| -- |
5.2.1 |
| Title |
MIMOLA |
| Miscellaneous information |
92 -- |
| -- |
5.2.2 |
| Title |
GNU C Compiler |
| Miscellaneous information |
94 -- |
| -- |
5.2.3 |
| Title |
Little C Compiler |
| Miscellaneous information |
94 -- |
| -- |
5.2.4 |
| Title |
CoSy |
| Miscellaneous information |
95 -- |
| -- |
5.3 |
| Title |
Processor Architecture Exploration |
| Miscellaneous information |
98 -- |
| -- |
5.3.1 |
| Title |
Methodology and Tools for ASIP Design |
| Miscellaneous information |
98 -- |
| -- |
5.3.2 |
| Title |
ADL-Based Approach |
| Miscellaneous information |
100 -- |
| -- |
5.4 |
| Title |
C Compiler Retargeting in the LISATek Platform |
| Miscellaneous information |
104 -- |
| -- |
5.4.2 |
| Title |
Register Allocator and Scheduler |
| Miscellaneous information |
105 -- |
| -- |
5.4.3 |
| Title |
Code Selector |
| Miscellaneous information |
107 -- |
| -- |
5.4.4 |
| Title |
Results |
| Miscellaneous information |
111 -- |
| -- |
6 |
| Title |
Automated Processor Configuration and Instruction Extension / |
| Statement of responsibility |
David Goodwin, Steve Leibson, Grant Martin |
| Miscellaneous information |
117 -- |
| -- |
6.1 |
| Title |
Automation Is Essential for ASIP Proliferation |
| Miscellaneous information |
118 -- |
| -- |
6.2 |
| Title |
The Tensilica Xtensa LX Configurable Processor |
| Miscellaneous information |
119 -- |
| -- |
6.3 |
| Title |
Generating ASIPs Using Xtensa |
| Miscellaneous information |
121 -- |
| -- |
6.4 |
| Title |
Automatic Generation of ASIP Specifications |
| Miscellaneous information |
123 -- |
| -- |
6.5 |
| Title |
Coding an Application for Automatic ASIP Generation |
| Miscellaneous information |
125 -- |
| -- |
6.6 |
| Title |
XPRES Benchmarking Results |
| Miscellaneous information |
126 -- |
| -- |
6.7 |
| Title |
Techniques for ASIP Generation |
| Miscellaneous information |
128 -- |
| -- |
6.7.1 |
| Title |
Reference Examples for Evaluating XPRES |
| Miscellaneous information |
128 -- |
| -- |
6.7.2 |
| Title |
VLIW-FLIX: Exploiting Instruction Parallelism |
| Miscellaneous information |
129 -- |
| -- |
6.7.3 |
| Title |
SIMD (Vectorization): Exploiting Data Parallelism |
| Miscellaneous information |
131 -- |
| -- |
6.7.4 |
| Title |
Operator Fusion: Exploiting Pipeline Parallelism |
| Miscellaneous information |
133 -- |
| -- |
6.7.5 |
| Title |
Combining Techniques |
| Miscellaneous information |
134 -- |
| -- |
6.8 |
| Title |
Exploring the Design Space |
| Miscellaneous information |
136 -- |
| -- |
6.9 |
| Title |
Evaluating Xpres Estimation Methods |
| Miscellaneous information |
137 -- |
| -- |
6.9.1 |
| Title |
Application Performance Estimation |
| Miscellaneous information |
139 -- |
| -- |
6.9.2 |
| Title |
ASIP Area Estimation |
| Miscellaneous information |
139 -- |
| -- |
6.9.3 |
| Title |
Characterization Benchmarks |
| Miscellaneous information |
140 -- |
| -- |
6.9.4 |
| Title |
Performance and Area Estimation |
| Miscellaneous information |
141 -- |
| -- |
7 |
| Title |
Automatic Instruction-Set Extensions / |
| Statement of responsibility |
Laura Pozzi, Paolo Ienne |
| Miscellaneous information |
145 -- |
| -- |
7.1 |
| Title |
Beyond Traditional Compilers |
| Miscellaneous information |
144 -- |
| -- |
7.1.1 |
| Title |
Structure of the Chapter |
| Miscellaneous information |
147 -- |
| -- |
7.2 |
| Title |
Building Block for Instruction Set Extension |
| Miscellaneous information |
147 -- |
| -- |
7.2.1 |
| Title |
Motivation |
| Miscellaneous information |
148 -- |
| -- |
7.2.2 |
| Title |
Problem Statement: Identification and Selection |
| Miscellaneous information |
148 -- |
| -- |
7.2.3 |
| Title |
Identification Algorithm |
| Miscellaneous information |
152 -- |
| -- |
7.2.4 |
| Title |
Results |
| Miscellaneous information |
155 -- |
| -- |
7.3 |
| Title |
Heuristics |
| Miscellaneous information |
160 -- |
| -- |
7.3.1 |
| Title |
Motivation |
| Miscellaneous information |
160 -- |
| -- |
7.3.2 |
| Title |
Types of Heuristic Algorithms |
| Miscellaneous information |
161 -- |
| -- |
7.3.3 |
| Title |
A Partitioning-Based Heuristic Algorithm |
| Miscellaneous information |
162 -- |
| -- |
7.3.4 |
| Title |
A Clustering Heuristic Algorithm |
| Miscellaneous information |
162 -- |
| -- |
7.4 |
| Title |
State-Holding Instruction-Set Extensions |
| Miscellaneous information |
163 -- |
| -- |
7.4.1 |
| Title |
Motivation |
| Miscellaneous information |
164 -- |
| -- |
7.4.2 |
| Title |
Local-Memory Identification Algorithm |
| Miscellaneous information |
165 -- |
| -- |
7.4.3 |
| Title |
Results |
| Miscellaneous information |
167 -- |
| -- |
7.5 |
| Title |
Exploiting Pipelining to Relax I/O Constraints |
| Miscellaneous information |
170 -- |
| -- |
7.5.1 |
| Title |
Motivation |
| Miscellaneous information |
171 -- |
| -- |
7.5.2 |
| Title |
Reuse of the Basic Identification Algorithm |
| Miscellaneous information |
173 -- |
| -- |
7.5.3 |
| Title |
Problem Statement: Pipelining |
| Miscellaneous information |
174 -- |
| -- |
7.5.4 |
| Title |
I/O Constrained Scheduling Algorithm |
| Miscellaneous information |
176 -- |
| -- |
7.5.5 |
| Title |
Results |
| Miscellaneous information |
177 -- |
| -- |
8 |
| Title |
Challenges to Automatic Customization / |
| Statement of responsibility |
Nigel Topham |
| Miscellaneous information |
185 -- |
| -- |
8.1 |
| Title |
The ARCompact Instruction Set Architecture |
| Miscellaneous information |
186 -- |
| -- |
8.1.1 |
| Title |
Mechanisms for Architecture Extension |
| Miscellaneous information |
190 -- |
| -- |
8.1.2 |
| Title |
ARCompact Implementations |
| Miscellaneous information |
190 -- |
| -- |
8.2 |
| Title |
Microarchitecture Challenges |
| Miscellaneous information |
191 -- |
| -- |
8.3 |
| Title |
Case Study-Entropy Decoding |
| Miscellaneous information |
193 -- |
| -- |
8.3.1 |
| Title |
Customizing VLD Extensions |
| Miscellaneous information |
195 -- |
| -- |
8.4 |
| Title |
Limitations of Automated Extension |
| Miscellaneous information |
203 -- |
| -- |
8.5 |
| Title |
The Benefits of Architecture Extension |
| Miscellaneous information |
205 -- |
| -- |
8.5.1 |
| Title |
Customization Enables CoDesign |
| Miscellaneous information |
205 -- |
| -- |
8.5.2 |
| Title |
Customization Offers Performance Headroom |
| Miscellaneous information |
206 -- |
| -- |
8.5.3 |
| Title |
Customization Enables Platform IP |
| Miscellaneous information |
206 -- |
| -- |
8.5.4 |
| Title |
Customization Enables Differentiation |
| Miscellaneous information |
207 -- |
| -- |
9 |
| Title |
Coprocessor Generation from Executable Code / |
| Statement of responsibility |
Richard Taylor, David Stewart |
| Miscellaneous information |
209 -- |
| -- |
9.2 |
| Title |
User Level Flow |
| Miscellaneous information |
210 -- |
| -- |
9.3 |
| Title |
Integration with Embedded Software |
| Miscellaneous information |
214 -- |
| -- |
9.4 |
| Title |
Coprocessor Architecture |
| Miscellaneous information |
215 -- |
| -- |
9.5 |
| Title |
ILP Extraction Challenges |
| Miscellaneous information |
218 -- |
| -- |
9.6 |
| Title |
Internal Tool Flow |
| Miscellaneous information |
220 -- |
| -- |
9.7 |
| Title |
Code Mapping Approach |
| Miscellaneous information |
225 -- |
| -- |
9.8 |
| Title |
Synthesizing Coprocessor Architectures |
| Miscellaneous information |
228 -- |
| -- |
9.9 |
| Title |
A Real-World Example |
| Miscellaneous information |
229 -- |
| -- |
10 |
| Title |
Datapath Synthesis / |
| Statement of responsibility |
Philip Brisk, Majid Sarrafzadeh |
| Miscellaneous information |
233 -- |
| -- |
10.2 |
| Title |
Custom Instruction Selection |
| Miscellaneous information |
234 -- |
| -- |
10.3 |
| Title |
Theoretical Preliminaries |
| Miscellaneous information |
236 -- |
| -- |
10.3.1 |
| Title |
The Minimum Area-Cost Acyclic Common Supergraph Problem |
| Miscellaneous information |
236 -- |
| -- |
10.3.2 |
| Title |
Subsequence and Substring Matching Techniques |
| Miscellaneous information |
237 -- |
| -- |
10.4 |
| Title |
Minimum Area-Cost Acyclic Common Supergraph Heuristic |
| Miscellaneous information |
238 -- |
| -- |
10.4.1 |
| Title |
Path-Based Resource Sharing |
| Miscellaneous information |
238 -- |
| -- |
10.4.3 |
| Title |
Pseudocode |
| Miscellaneous information |
240 -- |
| -- |
10.5 |
| Title |
Multiplexer Insertion |
| Miscellaneous information |
246 -- |
| -- |
10.5.1 |
| Title |
Unary and Binary Noncommutative Operators |
| Miscellaneous information |
246 -- |
| -- |
10.5.2 |
| Title |
Binary Commutative Operators |
| Miscellaneous information |
247 -- |
| -- |
10.6 |
| Title |
Datapath Synthesis |
| Miscellaneous information |
249 -- |
| -- |
10.6.1 |
| Title |
Pipelined Datapath Synthesis |
| Miscellaneous information |
249 -- |
| -- |
10.6.2 |
| Title |
High-Level Synthesis |
| Miscellaneous information |
249 -- |
| -- |
10.7 |
| Title |
Experimental Results |
| Miscellaneous information |
250 -- |
| -- |
11 |
| Title |
Instruction Matching and Modeling / |
| Statement of responsibility |
Sri Parameswaran, Jorg Henkel, Newton Cheung |
| Miscellaneous information |
257 -- |
| -- |
11.1 |
| Title |
Matching Instructions |
| Miscellaneous information |
259 -- |
| -- |
11.1.1 |
| Title |
Introduction to Binary Decision Diagrams |
| Miscellaneous information |
259 -- |
| -- |
11.1.2 |
| Title |
The Translator |
| Miscellaneous information |
261 -- |
| -- |
11.1.3 |
| Title |
Filtering Algorithm |
| Miscellaneous information |
264 -- |
| -- |
11.1.4 |
| Title |
Combinational Equivalence Checking Model |
| Miscellaneous information |
265 -- |
| -- |
11.1.5 |
| Title |
Results |
| Miscellaneous information |
265 -- |
| -- |
11.2 |
| Title |
Modeling |
| Miscellaneous information |
268 -- |
| -- |
11.2.2 |
| Title |
Customization Parameters |
| Miscellaneous information |
270 -- |
| -- |
11.2.3 |
| Title |
Characterization for Various Constraints |
| Miscellaneous information |
271 -- |
| -- |
11.2.4 |
| Title |
Equations for Estimating Area, Latency, and Power Consumption |
| Miscellaneous information |
273 -- |
| -- |
11.2.5 |
| Title |
Evaluation Results |
| Miscellaneous information |
274 -- |
| -- |
12 |
| Title |
Processor Verification / |
| Statement of responsibility |
Daniel Grosse, Robert Siegmund, Rolf Drechsler |
| Miscellaneous information |
281 -- |
| -- |
12.1 |
| Title |
Motivation |
| Miscellaneous information |
281 -- |
| -- |
12.2 |
| Title |
Overview of Verification Approaches |
| Miscellaneous information |
282 -- |
| -- |
12.2.1 |
| Title |
Simulation |
| Miscellaneous information |
282 -- |
| -- |
12.2.2 |
| Title |
Semiformal Techniques |
| Miscellaneous information |
284 -- |
| -- |
12.2.3 |
| Title |
Proof Techniques |
| Miscellaneous information |
284 -- |
| -- |
12.2.4 |
| Title |
Coverage |
| Miscellaneous information |
285 -- |
| -- |
12.3 |
| Title |
Formal Verification of a RISC CPU |
| Miscellaneous information |
285 -- |
| -- |
12.3.1 |
| Title |
Verification Approach |
| Miscellaneous information |
286 -- |
| -- |
12.3.2 |
| Title |
Specification |
| Miscellaneous information |
287 -- |
| -- |
12.3.3 |
| Title |
SystemC Model |
| Miscellaneous information |
288 -- |
| -- |
12.3.4 |
| Title |
Formal Verification |
| Miscellaneous information |
289 -- |
| -- |
12.4 |
| Title |
Verification Challenges in Customizable and Configurable Embedded Processors |
| Miscellaneous information |
293 -- |
| -- |
12.5 |
| Title |
Verification of Processor Peripherals |
| Miscellaneous information |
294 -- |
| -- |
12.5.1 |
| Title |
Coverage-Driven Verification Based on Constrained-Random Stimulation |
| Miscellaneous information |
294 -- |
| -- |
12.5.2 |
| Title |
Assertion-Based Verification of Corner Cases |
| Miscellaneous information |
297 -- |
| -- |
12.5.3 |
| Title |
Case Study: Verification of an On-Chip Bus Bridge |
| Miscellaneous information |
298 -- |
| -- |
13 |
| Title |
Sub-RISC Processors / |
| Statement of responsibility |
Andrew Mihal, Scott Weber, Kurt Keutzer |
| Miscellaneous information |
303 -- |
| -- |
13.1 |
| Title |
Concurrent Architectures, Concurrent Applications |
| Miscellaneous information |
303 -- |
| -- |
13.2 |
| Title |
Motivating Sub-RISC PEs |
| Miscellaneous information |
306 -- |
| -- |
13.2.1 |
| Title |
RISC PEs |
| Miscellaneous information |
307 -- |
| -- |
13.2.2 |
| Title |
Customizable Datapaths |
| Miscellaneous information |
311 -- |
| -- |
13.2.3 |
| Title |
Synthesis Approaches |
| Miscellaneous information |
311 -- |
| -- |
13.2.4 |
| Title |
Architecture Description Languages |
| Miscellaneous information |
311 -- |
| -- |
13.3 |
| Title |
Designing TIPI Processing Elements |
| Miscellaneous information |
316 -- |
| -- |
13.3.1 |
| Title |
Building Datapath Models |
| Miscellaneous information |
317 -- |
| -- |
13.3.2 |
| Title |
Operation |
| 505 00 - FORMATTED CONTENTS NOTE |
|---|
| Title |
Extraction |
| Miscellaneous information |
318 -- |
| -- |
13.3.3 |
| Title |
Single PE Simulator Generation |
| Miscellaneous information |
318 -- |
| -- |
13.3.4 |
| Title |
TIPI Multiprocessors |
| Miscellaneous information |
319 -- |
| -- |
13.3.5 |
| Title |
Multiprocessor Simulation and RTL Code Generation |
| Miscellaneous information |
321 -- |
| -- |
13.4 |
| Title |
Deploying Applications with Cairn |
| Miscellaneous information |
321 -- |
| -- |
13.4.1 |
| Title |
The Cairn Application Abstraction |
| Miscellaneous information |
323 -- |
| -- |
13.4.2 |
| Title |
Model Transforms |
| Miscellaneous information |
325 -- |
| -- |
13.4.3 |
| Title |
Mapping Models |
| Miscellaneous information |
325 -- |
| -- |
13.4.4 |
| Title |
Code Generation |
| Miscellaneous information |
326 -- |
| -- |
13.5 |
| Title |
IPv4 Forwarding Design Example |
| Miscellaneous information |
327 -- |
| -- |
13.5.1 |
| Title |
Designing a PE for Click |
| Miscellaneous information |
327 -- |
| -- |
13.5.2 |
| Title |
ClickPE Architecture |
| Miscellaneous information |
328 -- |
| -- |
13.5.3 |
| Title |
ClickPE Control Logic |
| Miscellaneous information |
329 -- |
| -- |
13.5.4 |
| Title |
LuleaPE Architecture |
| Miscellaneous information |
330 -- |
| -- |
13.6 |
| Title |
Performance Results |
| Miscellaneous information |
331 -- |
| -- |
13.6.1 |
| Title |
ClickPE Performance |
| Miscellaneous information |
332 -- |
| -- |
13.6.2 |
| Title |
LuleaPE Performance |
| Miscellaneous information |
333 -- |
| -- |
13.6.3 |
| Title |
Performance Comparison |
| Miscellaneous information |
334 -- |
| -- |
13.6.4 |
| Title |
Potentials for Improvement |
| Miscellaneous information |
335 -- |
| -- |
14 |
| Title |
Application Specific Instruction Set Processor for UMTS-FDD Cell Search / |
| Statement of responsibility |
Kimmo Puusaari, Timo Yli-Pietila, Kim Rounioja |
| Miscellaneous information |
339 -- |
| -- |
14.1 |
| Title |
ASIP on Wireless Modem Design |
| Miscellaneous information |
340 -- |
| -- |
14.1.1 |
| Title |
The Role of ASIP |
| Miscellaneous information |
340 -- |
| -- |
14.1.2 |
| Title |
ASIP Challenges for a System House |
| Miscellaneous information |
343 -- |
| -- |
14.1.3 |
| Title |
Potential ASIP Use Cases in Wireless Receivers |
| Miscellaneous information |
344 -- |
| -- |
14.2 |
| Title |
Functionality of Cell Search ASIP |
| Miscellaneous information |
346 -- |
| -- |
14.2.1 |
| Title |
Cell Search-Related Channels and Codes |
| Miscellaneous information |
346 -- |
| -- |
14.2.2 |
| Title |
Cell Search Functions |
| Miscellaneous information |
347 -- |
| -- |
14.2.3 |
| Title |
Requirements for the ASIP |
| Miscellaneous information |
347 -- |
| -- |
14.3 |
| Title |
Cell Search ASIP Design and Verification |
| Miscellaneous information |
348 -- |
| -- |
14.3.1 |
| Title |
Microarchitecture |
| Miscellaneous information |
348 -- |
| -- |
14.3.2 |
| Title |
Special Function Units |
| Miscellaneous information |
350 -- |
| -- |
14.3.3 |
| Title |
Instruction Set |
| Miscellaneous information |
353 -- |
| -- |
14.3.4 |
| Title |
HDL Generation |
| Miscellaneous information |
354 |
| 596 ## - |
|---|
| -- |
1 2 |
| 650 #0 - SUBJECT ADDED ENTRY--TOPICAL TERM |
|---|
| Topical term or geographic name entry element |
Embedded computer systems. |
| 650 #0 - SUBJECT ADDED ENTRY--TOPICAL TERM |
|---|
| Topical term or geographic name entry element |
Embedded computer systems |
| General subdivision |
Design and construction. |
| 700 1# - ADDED ENTRY--PERSONAL NAME |
|---|
| Personal name |
Ienne, Paolo. |
| 700 1# - ADDED ENTRY--PERSONAL NAME |
|---|
| Personal name |
Leupers, Rainer. |
| 830 #0 - SERIES ADDED ENTRY--UNIFORM TITLE |
|---|
| Uniform title |
Morgan Kaufmann series in systems on silicon. |
| 856 42 - ELECTRONIC LOCATION AND ACCESS |
|---|
| Materials specified |
Publisher description |
| Uniform Resource Identifier |
<a href="http://catdir.loc.gov/catdir/enhancements/fy0713/2007296561-d.html">http://catdir.loc.gov/catdir/enhancements/fy0713/2007296561-d.html</a> |
| 942 ## - ADDED ENTRY ELEMENTS (KOHA) |
|---|
| Koha item type |
Books |
| 994 ## - |
|---|
| -- |
Z0 |
| -- |
SUPMU |