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    Digital design and Verilog HDL fundamentals / (Record no. 2765)

    000 -LEADER
    fixed length control field 06602cam a2200361 a 4500
    001 - CONTROL NUMBER
    control field u5387
    003 - CONTROL NUMBER IDENTIFIER
    control field SA-PMU
    005 - DATE AND TIME OF LATEST TRANSACTION
    control field 20210418123355.0
    008 - FIXED-LENGTH DATA ELEMENTS--GENERAL INFORMATION
    fixed length control field 080320s2008 flua 001 0 eng
    010 ## - LIBRARY OF CONGRESS CONTROL NUMBER
    LC control number 2008012851
    040 ## - CATALOGING SOURCE
    Original cataloging agency DLC
    Language of cataloging eng
    Transcribing agency DLC
    Modifying agency BAKER
    -- YDXCP
    -- BTCTA
    -- C#P
    -- BWX
    -- CDX
    -- IXA
    -- OUP
    -- OCLCQ
    020 ## - INTERNATIONAL STANDARD BOOK NUMBER
    International Standard Book Number 9781420074154 (hardback : alk. paper)
    020 ## - INTERNATIONAL STANDARD BOOK NUMBER
    International Standard Book Number 1420074156 (hardback : alk. paper)
    035 ## - SYSTEM CONTROL NUMBER
    System control number (OCoLC)213601940
    Canceled/invalid control number (OCoLC)181142717
    050 00 - LIBRARY OF CONGRESS CALL NUMBER
    Classification number TK7868.D5
    Item number C3945 2008
    082 00 - DEWEY DECIMAL CLASSIFICATION NUMBER
    Classification number 621.39/5
    Edition number 22
    100 1# - MAIN ENTRY--PERSONAL NAME
    Personal name Cavanagh, Joseph J. F.
    245 10 - TITLE STATEMENT
    Title Digital design and Verilog HDL fundamentals /
    Statement of responsibility, etc. Joseph Cavanagh.
    260 ## - PUBLICATION, DISTRIBUTION, ETC.
    Place of publication, distribution, etc. Boca Raton :
    Name of publisher, distributor, etc. CRC Press,
    Date of publication, distribution, etc. c2008.
    300 ## - PHYSICAL DESCRIPTION
    Extent 1147 p. :
    Other physical details ill. ;
    Dimensions 27 cm.
    500 ## - GENERAL NOTE
    General note Includes index.
    505 0# - FORMATTED CONTENTS NOTE
    Formatted contents note Number systems, number representations, and codes -- Number systems -- Binary number system -- Octal number system -- Decimal number system -- Hexadecimal number system -- Arithmetic operations -- Conversion between radices -- Number representations -- Sign magnitude -- Diminished-radix complement -- Radix complement -- Arithmetic operations -- Binary codes -- Binary weighted and nonweighted codes -- Binary-to-BCD conversion -- BCD-to-binary conversion -- Gray code -- Error detection and correction codes -- Parity -- Hamming code -- Cyclic redundancy check code -- Checksum -- Two-out-of-five code -- Horizontal and vertical parity check -- Serial data transmission -- Problems -- Minimization of switching functions -- Boolean algebra -- Algebraic minimization -- Karnaugh maps -- Map-entered variables -- Quine-McCluskey algorithm -- Petrick algorithm -- Problems -- Combinational logic -- Logic primitive gates -- Wired-and and Wired-or operations -- Three-state logic -- Functionally complete gates -- Logic macro functions -- Multiplexers -- Decoders -- Encoders -- Comparators -- Analysis of combinational logic -- Synthesis of combinational logic -- Problems.
    505 0# - FORMATTED CONTENTS NOTE
    Formatted contents note Combinational logic design using verilog HDL -- Built-in primitives -- User-defined primitives -- Defining a user-defined primitive -- Combinational user-defined primitives -- Dataflow modeling -- Continuous assignment -- Reduction operators -- Conditional operator -- Relational operators -- Logical operators -- Bitwise operators -- Shift operators -- Behavioral modeling -- Initial statement -- Always statement -- Intrastatement delay -- Interstatement delay -- Blocking assignments -- Nonblocking assignments -- Conditional statement -- Case statement -- Loop statements -- Tasks -- Functions -- Structural modeling -- Module instantiation -- Ports -- Design examples 383 4.6 Problems -- Computer arithmetic -- Fixed-point addition -- Ripple-carry addition -- Carry lookahead addition -- Fixed-point subtraction -- Fixed-point multiplication -- Sequential add-shift -- Booth algorithm -- Bit-pair recoding -- Array multiplier -- Fixed-point division -- Restoring division -- Nonrestoring division -- Decimal addition -- Addition with sum correction -- Addition using multiplexers for sum correction -- Decimal subtraction -- Decimal multiplication -- Multiplication using read-only memory -- Decimal division -- Division using table lookup -- Floating-point arithmetic -- Floating-point addition/subtraction -- Floating-point multiplication -- Floating-point division -- Rounding methods -- Problems -- Computer arithmetic design using verilog HDL -- Fixed-point addition -- High-speed full adder -- Four-bit ripple adder -- Carry lookahead adder -- Fixed-point subtraction -- Fixed-point multiplication -- Booth algorithm -- Array multiplier -- Decimal addition -- BCD addition with sum correction -- BCD addition using multiplexers for sum correction -- Decimal subtraction -- Problems.
    505 0# - FORMATTED CONTENTS NOTE
    Formatted contents note Sequential logic -- Analysis of synchronous sequential machines -- Machine alphabets -- Storage elements -- Classes of sequential machines -- Methods of analysis -- Analysis examples -- Synthesis of synchronous sequential machines -- Synthesis procedure -- Synchronous registers -- Synchronous counters -- Moore machines -- Mealy machines -- Output glitches -- Analysis of asynchronous sequential machines -- Fundamental-mode model -- Methods of analysis -- Hazards -- Oscillations -- Races -- Synthesis of asynchronous sequential machines -- Synthesis procedure -- Synthesis examples -- Analysis of pulse-mode asynchronous sequential machines -- Analysis procedure -- Synthesis of pulse-mode ssynchronous sequential machines -- Synthesis procedure -- Problems -- Sequential logic design using verilog HDL -- Synchronous sequential machines -- Asynchronous sequential machines -- Pulse-mode ssynchronous sequential machines -- Problems -- Programmable logic devices -- Programmable read-only memory -- Combinational logic -- Sequential logic -- Programmable array logic -- Combinational logic -- Sequential logic -- Programmable logic arrays -- Combinational logic -- Sequential logic -- Field-programmable gate arrays -- Problems.
    505 0# - FORMATTED CONTENTS NOTE
    Formatted contents note Digital and analog conversion -- Operational amplifier -- Digital-to-analog conversion -- Binary-weighted resistor network digital-to-analog converter -- R-2R resistor network digital-to-analog converter -- Analog-to-digital conversion -- Comparators -- Counter analog-to-digital converter -- Successive approximation analog-to-tigital converter -- Simultaneous analog-to digital converter -- Problems -- Magnetic recording fundamentals -- Return to zero -- Nonreturn to zero -- Nonreturn to zero inverted -- Frequency modulation -- Phase encoding -- Modified frequency modulation -- Run-length limited -- Group-coded recording -- Peak shift -- Write precompensation -- Vertical recording -- Problems -- Additional topics in digital design -- Functional decomposition -- Iterative networks -- Hamming code -- Cyclic redundancy check code -- Residue checking -- Parity prediction -- Condition codes for addition -- Arithmetic and logic unit -- Memory -- Problems -- Appendix A: event queue -- Event handling for dataflow assignments -- Event handling for blocking assignments -- Event handling for nonblocking assignments -- Event handling for mixed blocking and nonblocking assignments -- Appendix B: verilog project procedure -- Appendix C: answers to select problems.
    596 ## -
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    650 #0 - SUBJECT ADDED ENTRY--TOPICAL TERM
    Topical term or geographic name entry element Logic circuits
    General subdivision Computer-aided design.
    650 #0 - SUBJECT ADDED ENTRY--TOPICAL TERM
    Topical term or geographic name entry element Verilog (Computer hardware description language)
    650 #0 - SUBJECT ADDED ENTRY--TOPICAL TERM
    Topical term or geographic name entry element Digital electronics.
    856 41 - ELECTRONIC LOCATION AND ACCESS
    Materials specified Table of contents only
    Uniform Resource Identifier <a href="http://catdir.loc.gov/catdir/toc/ecip0814/2008012851.html">http://catdir.loc.gov/catdir/toc/ecip0814/2008012851.html</a>
    942 ## - ADDED ENTRY ELEMENTS (KOHA)
    Koha item type Books
    994 ## -
    -- Z0
    -- SUPMU
    Holdings
    Withdrawn status Lost status Source of classification or shelving scheme Damaged status Not for loan Home library Current library Date acquired Total Checkouts Full call number Barcode Date last seen Copy number Price effective from Koha item type Public note
              Main Library Main Library 04/18/2021   TK7868 .D5 C3945 2008 51952000126041 04/15/2021 1 04/15/2021 Books STACKS