VLSI test principles and architectures :  design for testability / 
edited by Laung-Terng Wang, Cheng-Wen Wu, Xiaoqing Wen. 
 - Amsterdam ;  Boston :  Elsevier Morgan Kaufmann Publishers,  c2006. 
 - xxx, 777 p. :  ill. ;  25 cm. 
 - The Morgan Kaufmann series in systems on silicon .
 - Morgan Kaufmann series in systems on silicon. .
<br/><br/>Includes bibliographical references and index. 
<br/><br/>Design for testability / Laung-Terng (L.-T.) Wang, Xiaoqing Wen, and Khader S. Abdel-Hafez -- Logic and fault simulation / Jiun-Lang Huang, James C.-M. Li, and Duncan M. (Hank) Walker -- Test generation / Michael S. Hsiao -- Logic built-in self-test / Laung-Terng (L.-T.) Wang -- Test compression / Xiaowei Li, Kuen-Jong Lee, and Nur A. Touba -- Logic diagnosis / Shi-Yu Huang -- Memory testing and built-in self-test / Cheng-Wen Wu -- Memory diagnosis and built-in self-repair / Cheng-Wen Wu -- Boundary scan and core-based testing / Kuen-Jong Lee -- Analog and mixed-signal testing / Chauchin Su -- Test technology trends in the nanometer age / Kwang-Ting (Tim) Cheng, Wen-Ben Jone, and Laung-Terng (L.-T.) Wang. 
<br/><br/><label>ISBN: </label>0123705975 (hardcover : alk. paper) 9780123705976 (hardcover : alk. paper) 
<br/><br/><label>LCCN: </label>2006006869 
<br/><br/><label>Subjects--Topical Terms: </label><br/>Integrated circuits--Very large scale integration--Testing.<br/>Integrated circuits--Very large scale integration--Design.
<br/><br/><label>LC Class. No.: </label>TK7874.75  / .V587 2006 
<br/><br/><label>Dewey Class. No.: </label>621.39/5