TY  - BOOK
AU  - Wang,Laung-Terng
AU  - Wu,Cheng-Wen
AU  - Wen,Xiaoqing
TI  - VLSI test principles and architectures: design for testability 
T2  - The Morgan Kaufmann series in systems on silicon
SN  - 0123705975 (hardcover : alk. paper)
AV  - TK7874.75 .V587 2006
U1  - 621.39/5 22
PY  - 2006///
CY  - Amsterdam, Boston
PB  - Elsevier Morgan Kaufmann Publishers
KW  - Integrated circuits
KW  - Very large scale integration
KW  - Testing
KW  - Design
N1  - Includes bibliographical references and index; Design for testability / Laung-Terng (L.-T.) Wang, Xiaoqing Wen, and Khader S. Abdel-Hafez -- Logic and fault simulation / Jiun-Lang Huang, James C.-M. Li, and Duncan M. (Hank) Walker -- Test generation / Michael S. Hsiao -- Logic built-in self-test / Laung-Terng (L.-T.) Wang -- Test compression / Xiaowei Li, Kuen-Jong Lee, and Nur A. Touba -- Logic diagnosis / Shi-Yu Huang -- Memory testing and built-in self-test / Cheng-Wen Wu -- Memory diagnosis and built-in self-repair / Cheng-Wen Wu -- Boundary scan and core-based testing / Kuen-Jong Lee -- Analog and mixed-signal testing / Chauchin Su -- Test technology trends in the nanometer age / Kwang-Ting (Tim) Cheng, Wen-Ben Jone, and Laung-Terng (L.-T.) Wang
UR  - http://catdir.loc.gov/catdir/toc/ecip069/2006006869.html
UR  - http://catdir.loc.gov/catdir/enhancements/fy0632/2006006869-d.html
ER  -