TY  - BOOK
AU  - Wile,Bruce
AU  - Goss,John C.
AU  - Roesner,W.
TI  - Comprehensive functional verification the complete industry cycle
SN  - 0127518037
AV  - TK7874.58 .W55 2005
U1  - 621.3815/48 22
PY  - 2005///
CY  - Amsterdam, Boston
PB  - Elsevier/Morgan Kaufmann
KW  - Integrated circuits
KW  - Verification
KW  - Computer engineering
N1  - Includes bibliographical references (p. 657-662) and index; Part I; Introduction to Verification --; 1; Verification in the Chip Design Process; 5 --; 1.1; Introduction to Functional Verification; 5 --; 1.2; The Verification Challenge; 8 --; 1.2.1; The Challenge of State Space Explosion; 9 --; 1.2.2; The Challenge of Detecting Incorrect Behavior; 12 --; 1.3; Mission and Goals of Verification; 14 --; 1.3.1; Verification Engineer "Musts"; 18 --; 1.4; Cost of Verification; 20 --; 1.4.1; Engineering Costs and the Need for an Independent Verification Team; 20 --; 1.4.2; Design Automation Tools; 21 --; 1.4.3; Time; 22 --; 1.5; Areas of Verification Beyond the Scope of this Book; 23 --; 1.6; The Verification Cycle: A Structured Process; 24 --; 1.6.1; Functional Specification; 25 --; 1.6.2; Create Verification Plan; 26 --; 1.6.3; Develop Environment; 27 --; 1.6.4; Debug HDL and Environment; 27 --; 1.6.5; Regression; 28 --; 1.6.6; Fabricate Hardware; 28 --; 1.6.7; Debug Fabricated Hardware (Systems Test); 29 --; 1.6.8; Escape Analysis; 29 --; 1.6.9; Common Verification Cycle Breakdowns; 30 --; 2; Verification Flow; 35 --; 2.1; Verification Hierarchy; 35 --; 2.1.1; Levels of Verification; 36 --; 2.1.2; What Level to Choose?; 41 --; 2.2; Strategy of Verification; 45 --; 2.2.1; Driving Principles; 45 --; 2.2.2; Checking Strategies; 50 --; 2.2.3; Checking the Black Box; 55 --; 2.2.5; The General Simulation Environment; 61 --; 2.2.6; Verification Methodology Evolution; 62 --; 3; Fundamentals of Simulation Based Verification; 73 --; 3.1; Basic Verification Environment: A Test Bench; 73 --; 3.1.1; Stimulus Component; 74 --; 3.1.2; Monitor; 80 --; 3.1.3; Checker; 82 --; 3.1.4; Scoreboard; 83 --; 3.1.5; Design Under Verification; 85 --; 3.2; Observation Points: Black-Box, White-Box and Grey-Box Verification; 86 --; 3.2.1; Black Box; 86 --; 3.2.2; White Box; 87 --; 3.2.3; Grey Box; 88 --; 3.3; Assertion Based Verification-An Overview; 89 --; 3.3.1; The Importance of Assertions; 90 --; 3.3.2; Assertions Express Design Intent; 92 --; 3.3.3; Classification of Assertions; 94 --; 3.4; Test Benches and Testing Strategies; 95 --; 3.4.1; Deterministic Test Benches; 95 --; 3.4.2; Self-Checking Test Benches; 97 --; 4; The Verification Plan; 103 --; 4.1; The Functional Specification; 103 --; 4.2; The Evolution of the Verification Plan; 104 --; 4.3; Contents of the Verification Plan; 106 --; 4.3.1; Description of Verification Levels; 106 --; 4.3.2; Required Tools; 107 --; 4.3.3; Risks and Dependencies; 108 --; 4.3.4; Functions to be Verified; 109 --; 4.3.5; Specific Tests and Methods: Environment; 111 --; 4.3.6; Coverage Requirements; 115 --; 4.3.7; Test Case Scenarios: Matrix; 116 --; 4.3.8; Resource Requirements; 117 --; 4.3.9; Schedule Details; 118 --; 4.4; Verification Example: Calc1; 121 --; 4.4.1; Design Description; 121 --; 4.4.2; Creating the Verification Plan for Calc1; 125 --; 4.4.3; Deterministic Verification of Calc1; 131 --; Part II; Simulation Based Verification --; 5; HDLs and Simulation Engines; 141 --; 5.1; Hardware Description Languages; 143 --; 5.1.1; HDL Modeling Levels; 143 --; 5.1.2; Verification Aspects of HDLs; 153 --; 5.2; Simulation Engines: Introduction; 159 --; 5.2.1; Speed versus Accuracy; 160 --; 5.2.2; Making the Right Methodology Choices; 162 --; 5.3; Event-Driven Simulation; 162 --; 5.3.1; Hierarchical Model Network; 163 --; 5.3.2; Model Evaluation Over Time; 165 --; 5.3.3; Event-Driven Control of Model Evaluation; 167 --; 5.3.4; Implementation Sketch of an Event-Driven Simulation Engine; 172 --; 5.4; Improving Simulation Throughput; 178 --; 5.5; Cycle-Based Simulation; 182 --; 5.5.1; Synchronous Design; 183 --; 5.5.2; The Cycle-Based Simulation Algorithm; 184 --; 5.5.3; Extensions to Basic Cycle-Based Simulation Engines; 188 --; 5.6; Waveform Viewers; 191 --; 6; Creating Environments; 199 --; 6.1; Test Bench Writing Tools; 200 --; 6.1.1; HDL Languages as Test Bench Tool; 201 --; 6.1.2; C/C++ Libraries; 207 --; 6.1.3; High-Level Verification Languages; 230 --; 6.1.4; Other Test Bench Tools; 241 --; 6.2; Verification Coverage; 243 --; 6.2.2; Functional Verification Test Coverage versus Manufacturing Test Coverage; 246 --; 6.2.3; Structural Coverage; 247 --; 6.2.4; Functional Coverage; 251 --; 6.2.5; Coverage Bulk Data Collection and Management; 254 --; 6.2.6; The Right Coverage Analysis Strategy; 255 --; 7; Strategies for Simulation-Based Stimulus Generation; 259 --; 7.1; Calc2 Overview; 260 --; 7.1.1; Calc2 Verification Plan; 263 --; 7.1.2; Calc2 and the Strategies for Stimulus Generation; 269 --; 7.2; Strategies for Stimulus Generation; 270 --; 7.2.1; Types of Stimulus Generation; 270 --; 7.2.2; General Algorithms for Stimulus Components; 275 --; 7.2.3; Applying the Four Types of Stimulus Generation to Calc2; 277 --; 7.2.4; Seeding Random Test Cases; 294 --; 7.2.5; Constraint Solving in Random Environments; 297 --; 7.2.6; Coverage Techniques in Random Environments; 301 --; 7.2.7; Making Rare Events Occur; 303 --; 7.2.8; Stimulus Generation of Deadlocks and Livelocks; 306 --; 8; Strategies for Results Checking in Simulation-Based Verification; 313 --; 8.1; Types of Result Checking; 313 --; 8.1.1; On-the-Fly Checking versus End-of-Test Case Checking; 314 --; 8.1.2; Pregenerated Test Cases versus On-the-Fly Generated Test Cases; 321 --; 8.1.3; Applying the Checking Strategies to Calc2; 322 --; 8.2; Debug; 334 --; 8.2.1; Debug Process; 336 --; 8.2.2; How Different Types of Test Benches Affect Debug; 349 --; 9; Pervasive Function Verification; 355 --; 9.1; System Reset and Bring-Up; 356 --; 9.1.1; Reset Line Initialization; 357 --; 9.1.2; Scan Initialization; 361 --; 9.1.3; Testability and Built-In Self-Test; 363 --; 9.2; Error and Degraded Mode Handling; 368 --; 9.2.1; Verifying Error Detection; 368 --; 9.2.2; Verifying Self-Healing Hardware; 372 --; 9.3; Verifying Hardware Debug Assists; 380 --; 9.3.1; Verifying Scan Ring Dumps; 381 --; Low Power Mode Verification; 384 --; 9.4.1; Power Savings Through Disabling Functional Units; 385 --; 9.4.2; Power Savings Through Cycle Time Degradation; 387 --; 10; Re-Use Strategies and System Simulation; 391 --; 10.1; Re-Use Strategies; 392 --; 10.1.1; Guidelines for Re-Use; 395 --; 10.1.2; Horizontal Re-Use; 403 --; 10.1.3; Vertical Re-Use; 404 --; 10.1.4; Applying Re-Use to Calc2; 405 --; 10.1.5; Assertion Re-Use; 410 --; 10.2; System Simulation; 412 --; 10.2.1; System Test Bench; 412 --; 10.2.2; Connectivity and Interaction of Units; 414 --; 10.2.3; Verification Challenges in a Re-Usable IP World; 418 --; 10.3; Beyond General-Purpose Logic Simulation; 420 --; 10.3.1; Acceleration; 421 --; 10.3.2; Emulation; 427 --; 10.3.3; Hardware/Software Co-verification; 428 --; 10.3.4; Co-simulation; 430 --; Part III; Formal Verification --; 11; Introduction to Formal Verification; 439 --; 11.1.1; Design Correctness and Specifications; 441 --; 11.1.2; Computational Complexity; 443 --; 11.1.3; The Myth of Linear Scaling of Simulation; 445 --; 11.1.4; Mathematical Proof Methods in Formal Verification; 446 --; 11.2; Formal Boolean Equivalence Checking; 448 --; 11.2.1; The Role of Equivalence Checking in the VLSI Design Flow; 449 --; 11.2.2; Main Elements of an Equivalence Checker Tool; 450 --; 11.2.3; Sequential and Combinational Boolean Equivalence Checking; 451 --; 11.2.4; Core Algorithms for Combinational Equivalence Checking; 454 --; 11.2.5; Blueprint of a Modern Equivalence Checking Tool; 465 --; 11.3; Functional Formal Verification-Property Checking; 467 --; 11.3.1; Property Checking vs.; Sequential Equivalence Checking; 468 --; 11.3.2; The Myth of Complete Verification with FV; 470 --; 11.3.3; Properties for an Example Design; 471 --; 11.3.4; DUV Drivers for Formal Verification; 476 --; 11.3.5; State Space Traversal and Temporal Logic; 479 --; 11.3.6; Functional Formal Verification Tool Flow; 483 --; 12; Using Formal Verification; 487 --; 12.1; Property Specification Using an HDL Library; 488 --; 12.1.1; The Open Verification Library (OVL); 489 --; 12.1.2; Using OVL to Specify Properties; 495 --; 12.2; The Property Specification Language PSL; 499 --; 12.2.2; The Boolean Layer of PSL; 501 --; 12.2.3; The Temporal Layer of PSL; 504 --; 12.2.4; The Verification Layer of PSL; 508 --; 12.2.5; The Modeling Layer of PSL; 511 --; 12.2.6; Using PSL to Specify Properties; 512 --; 12.2.7; Advanced PSL Topics and Caveats; 514 --; 12.3; Property Checking Using Formal Verification; 521 --; 12.3.1; Property Re-Use between Simulation and FV; 521 --; 12.3.2; Model Compliation; 522 --; 12.3.3; Formal Functional Verification Algorithms; 523 --; 12.3.4; Solutions to Address the Problem of State Space Explosion; 527 --; 12.3.5; Semi-Formal Verification; 530 --; 12.3.6; EDA Vendors Supplying Formal and Semi-Formal Verification Tools; 532 --; Part IV; Comprehensive Verification --; 13; Completing the Verification Cycle; 539 --; 13.1; Regression; 540 --; 13.1.1; Regression in the Verification Flow; 540 --; 13.1.2; Regression Quality; 542 --; 13.1.3; Regression Efficiency; 543 --; 13.2; Problem Tracking; 548 --; 13.3; Tape-Out Readiness; 552 --; 13.3.1; Metrics; 552 --; 13.3.2; Completion Criteria; 557 --; 13.4; Escape Analysis; 559 --; 13.4.1; Individual Bug Analysis; 561 --; 13.4.2; Escape Examples; 569 --; 13.4.3; Escape Analysis Trends; 572 --; 14; Advanced Verification Techniques; 579 --; 14.1; Save Verification Cycles-Bootstrapping the Verification Process; 580 --; 14.1.1; Separating POR and Mainline Verification; 580 --; 14.1.2; Bootstrapping the DUV into High-Potential States; 583 --; 14.1.3; Manipulating the DUV Specification Provoking States of Resource Conflict; 585 --; 14.2; High-Level Modeling-Concepts; 586 --; 14.2.1; Applications of the High-Level Model; 587 --; 14.2.2; High-Level Modeling Styles; 590 --; 14.3; Coverage-Directed Generation; 595 --; 15.1; The Line Delete Escape; 603 --; 15.1.1; The Background; 603 --; 15.1.2; The Verification Environments; 605 --; 15.1.3; The Escape; 607 --; 15.2; Branch History Table; 608
N2  - A key strength of this book is that it describes the entire verification cycle and details each stage. The organization of the book follows the cycle, demonstrating how functional verification engages all aspects of the overall design effort and how individual cycle stages relate to the larger design process. Throughout the text, the authors leverage their 35 plus years experience in functional verification, providing examples and case studies, and focusing on the skills, methods, and tools needed to complete each verification task. Additionally, the major vendors (Mentor Graphics, Cadence Design Systems, Verisity, and Synopsys) have implemented key examples from the text and made these available on line, so that the reader can test out the methods described in the text
UR  - http://catdir.loc.gov/catdir/enhancements/fy0627/2005299338-d.html
UR  - http://catdir.loc.gov/catdir/enhancements/fy0627/2005299338-t.html
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