Customizable embedded processors : design technologies and applications /
Paolo Ienne and Rainer Leupers [editors].
- San Francisco, Calif. : Oxford : Morgan Kaufmann ; Elsevier Science [distributor], 2006.
- xxviii, 497 p. : ill. ; 25 cm.
- Morgan Kaufmann series in systems on silicon .
- Morgan Kaufmann series in systems on silicon. .
Includes bibliographical references (p. [465]-484) and index.
In Praise of Customizable Embedded Processors Opportunities and Challenges -- From Pret-a-Porter to Tailor-Made / The Call for Flexibility Cool Chips for Shallow Pockets A Million Processors for the Price of One? Processors Coming of Age Travel Broadens the Mind Opportunities for Application-Specific Processors: The Case of Wireless Communications / Future Mobile Communication Systems Heterogeneous MPSoC for Digital Receivers The Fundamental Tradeoff between Energy Efficiency and Flexibility How to Exploit the Huge Design Space? Canonical Receiver Structure Analyzing and Classifying the Functions of a Digital Receiver Exploiting Parallelism ASIP Design Processor Design Flow Architecture Description Language Based Design Too Much Automation Is Bad Processor Design: The LISATek Approach Design Competence Rules the World Application-Specific or Domain-Specific Processors? Customizing Processors: Lofty Ambitions, Stark Realities / The "CFP" project at HP Labs Searching for the Best Architecture Is Not a Machine-Only Endeavor Designing a CPU Core Still Takes a Very Long Time Don't Underestimate Competitive Technologies Software Developers Don't Always Help You The Embedded World Is Not Immune to Legacy Problems Customization Can Be Trouble Aspects of Processor Customization -- Architecture Description Languages / ADLs and other languages Survey of Contemporary ADLs Content-Oriented Classification of ADLs Objective-Based Classification of ADLs C Compiler Retargeting / Compiler Construction Background Source Language Frontend Intermediate Representation and Optimization Machine Code Generation Approaches to Retargetable Compilation MIMOLA GNU C Compiler Little C Compiler CoSy Processor Architecture Exploration Methodology and Tools for ASIP Design ADL-Based Approach C Compiler Retargeting in the LISATek Platform Register Allocator and Scheduler Code Selector Results Automated Processor Configuration and Instruction Extension / Automation Is Essential for ASIP Proliferation The Tensilica Xtensa LX Configurable Processor Generating ASIPs Using Xtensa Automatic Generation of ASIP Specifications Coding an Application for Automatic ASIP Generation XPRES Benchmarking Results Techniques for ASIP Generation Reference Examples for Evaluating XPRES VLIW-FLIX: Exploiting Instruction Parallelism SIMD (Vectorization): Exploiting Data Parallelism Operator Fusion: Exploiting Pipeline Parallelism Combining Techniques Exploring the Design Space Evaluating Xpres Estimation Methods Application Performance Estimation ASIP Area Estimation Characterization Benchmarks Performance and Area Estimation Automatic Instruction-Set Extensions / Beyond Traditional Compilers Structure of the Chapter Building Block for Instruction Set Extension Motivation Problem Statement: Identification and Selection Identification Algorithm Results Heuristics Motivation Types of Heuristic Algorithms A Partitioning-Based Heuristic Algorithm A Clustering Heuristic Algorithm State-Holding Instruction-Set Extensions Motivation Local-Memory Identification Algorithm Results Exploiting Pipelining to Relax I/O Constraints Motivation Reuse of the Basic Identification Algorithm Problem Statement: Pipelining I/O Constrained Scheduling Algorithm Results Challenges to Automatic Customization / The ARCompact Instruction Set Architecture Mechanisms for Architecture Extension ARCompact Implementations Microarchitecture Challenges Case Study-Entropy Decoding Customizing VLD Extensions Limitations of Automated Extension The Benefits of Architecture Extension Customization Enables CoDesign Customization Offers Performance Headroom Customization Enables Platform IP Customization Enables Differentiation Coprocessor Generation from Executable Code / User Level Flow Integration with Embedded Software Coprocessor Architecture ILP Extraction Challenges Internal Tool Flow Code Mapping Approach Synthesizing Coprocessor Architectures A Real-World Example Datapath Synthesis / Custom Instruction Selection Theoretical Preliminaries The Minimum Area-Cost Acyclic Common Supergraph Problem Subsequence and Substring Matching Techniques Minimum Area-Cost Acyclic Common Supergraph Heuristic Path-Based Resource Sharing Pseudocode Multiplexer Insertion Unary and Binary Noncommutative Operators Binary Commutative Operators Datapath Synthesis Pipelined Datapath Synthesis High-Level Synthesis Experimental Results Instruction Matching and Modeling / Matching Instructions Introduction to Binary Decision Diagrams The Translator Filtering Algorithm Combinational Equivalence Checking Model Results Modeling Customization Parameters Characterization for Various Constraints Equations for Estimating Area, Latency, and Power Consumption Evaluation Results Processor Verification / Motivation Overview of Verification Approaches Simulation Semiformal Techniques Proof Techniques Coverage Formal Verification of a RISC CPU Verification Approach Specification SystemC Model Formal Verification Verification Challenges in Customizable and Configurable Embedded Processors Verification of Processor Peripherals Coverage-Driven Verification Based on Constrained-Random Stimulation Assertion-Based Verification of Corner Cases Case Study: Verification of an On-Chip Bus Bridge Sub-RISC Processors / Concurrent Architectures, Concurrent Applications Motivating Sub-RISC PEs RISC PEs Customizable Datapaths Synthesis Approaches Architecture Description Languages Designing TIPI Processing Elements Building Datapath Models Operation Paolo Ienne, Rainer Leupers Gerd Ascheid, Heinrich Meyr Joseph A. Fisher, Paolo Faraboschi, Cliff Young Prabhat Mishra, Nikil Dutt Rainer Leupers David Goodwin, Steve Leibson, Grant Martin Laura Pozzi, Paolo Ienne Nigel Topham Richard Taylor, David Stewart Philip Brisk, Majid Sarrafzadeh Sri Parameswaran, Jorg Henkel, Newton Cheung Daniel Grosse, Robert Siegmund, Rolf Drechsler Andrew Mihal, Scott Weber, Kurt Keutzer i -- Part I 1 3 -- 1.1 4 -- 1.2 5 -- 1.3 5 -- 1.4 7 -- 1.6 9 -- 2 11 -- 2.1 12 -- 2.2 14 -- 2.2.1 14 -- 2.2.2 17 -- 2.2.3 19 -- 2.2.4 21 -- 2.2.5 25 -- 2.3 26 -- 2.3.1 26 -- 2.3.2 28 -- 2.3.3 29 -- 2.3.4 30 -- 2.3.5 33 -- 2.3.6 35 -- 3 39 -- 3.1 41 -- 3.2 45 -- 3.3 46 -- 3.4 48 -- 3.5 49 -- 3.6 51 -- 3.7 52 -- Part II 4 59 -- 4.1 60 -- 4.2 62 -- 4.2.1 62 -- 4.2.2 72 -- 5 77 -- 5.1 79 -- 5.1.1 79 -- 5.1.2 80 -- 5.1.3 83 -- 5.2 91 -- 5.2.1 92 -- 5.2.2 94 -- 5.2.3 94 -- 5.2.4 95 -- 5.3 98 -- 5.3.1 98 -- 5.3.2 100 -- 5.4 104 -- 5.4.2 105 -- 5.4.3 107 -- 5.4.4 111 -- 6 117 -- 6.1 118 -- 6.2 119 -- 6.3 121 -- 6.4 123 -- 6.5 125 -- 6.6 126 -- 6.7 128 -- 6.7.1 128 -- 6.7.2 129 -- 6.7.3 131 -- 6.7.4 133 -- 6.7.5 134 -- 6.8 136 -- 6.9 137 -- 6.9.1 139 -- 6.9.2 139 -- 6.9.3 140 -- 6.9.4 141 -- 7 145 -- 7.1 144 -- 7.1.1 147 -- 7.2 147 -- 7.2.1 148 -- 7.2.2 148 -- 7.2.3 152 -- 7.2.4 155 -- 7.3 160 -- 7.3.1 160 -- 7.3.2 161 -- 7.3.3 162 -- 7.3.4 162 -- 7.4 163 -- 7.4.1 164 -- 7.4.2 165 -- 7.4.3 167 -- 7.5 170 -- 7.5.1 171 -- 7.5.2 173 -- 7.5.3 174 -- 7.5.4 176 -- 7.5.5 177 -- 8 185 -- 8.1 186 -- 8.1.1 190 -- 8.1.2 190 -- 8.2 191 -- 8.3 193 -- 8.3.1 195 -- 8.4 203 -- 8.5 205 -- 8.5.1 205 -- 8.5.2 206 -- 8.5.3 206 -- 8.5.4 207 -- 9 209 -- 9.2 210 -- 9.3 214 -- 9.4 215 -- 9.5 218 -- 9.6 220 -- 9.7 225 -- 9.8 228 -- 9.9 229 -- 10 233 -- 10.2 234 -- 10.3 236 -- 10.3.1 236 -- 10.3.2 237 -- 10.4 238 -- 10.4.1 238 -- 10.4.3 240 -- 10.5 246 -- 10.5.1 246 -- 10.5.2 247 -- 10.6 249 -- 10.6.1 249 -- 10.6.2 249 -- 10.7 250 -- 11 257 -- 11.1 259 -- 11.1.1 259 -- 11.1.2 261 -- 11.1.3 264 -- 11.1.4 265 -- 11.1.5 265 -- 11.2 268 -- 11.2.2 270 -- 11.2.3 271 -- 11.2.4 273 -- 11.2.5 274 -- 12 281 -- 12.1 281 -- 12.2 282 -- 12.2.1 282 -- 12.2.2 284 -- 12.2.3 284 -- 12.2.4 285 -- 12.3 285 -- 12.3.1 286 -- 12.3.2 287 -- 12.3.3 288 -- 12.3.4 289 -- 12.4 293 -- 12.5 294 -- 12.5.1 294 -- 12.5.2 297 -- 12.5.3 298 -- 13 303 -- 13.1 303 -- 13.2 306 -- 13.2.1 307 -- 13.2.2 311 -- 13.2.3 311 -- 13.2.4 311 -- 13.3 316 -- 13.3.1 317 -- 13.3.2 Extraction Single PE Simulator Generation TIPI Multiprocessors Multiprocessor Simulation and RTL Code Generation Deploying Applications with Cairn The Cairn Application Abstraction Model Transforms Mapping Models Code Generation IPv4 Forwarding Design Example Designing a PE for Click ClickPE Architecture ClickPE Control Logic LuleaPE Architecture Performance Results ClickPE Performance LuleaPE Performance Performance Comparison Potentials for Improvement Application Specific Instruction Set Processor for UMTS-FDD Cell Search / ASIP on Wireless Modem Design The Role of ASIP ASIP Challenges for a System House Potential ASIP Use Cases in Wireless Receivers Functionality of Cell Search ASIP Cell Search-Related Channels and Codes Cell Search Functions Requirements for the ASIP Cell Search ASIP Design and Verification Microarchitecture Special Function Units Instruction Set HDL Generation Kimmo Puusaari, Timo Yli-Pietila, Kim Rounioja 318 -- 13.3.3 318 -- 13.3.4 319 -- 13.3.5 321 -- 13.4 321 -- 13.4.1 323 -- 13.4.2 325 -- 13.4.3 325 -- 13.4.4 326 -- 13.5 327 -- 13.5.1 327 -- 13.5.2 328 -- 13.5.3 329 -- 13.5.4 330 -- 13.6 331 -- 13.6.1 332 -- 13.6.2 333 -- 13.6.3 334 -- 13.6.4 335 -- 14 339 -- 14.1 340 -- 14.1.1 340 -- 14.1.2 343 -- 14.1.3 344 -- 14.2 346 -- 14.2.1 346 -- 14.2.2 347 -- 14.2.3 347 -- 14.3 348 -- 14.3.1 348 -- 14.3.2 350 -- 14.3.3 353 -- 14.3.4 354
0123695260 9780123695260
2007296561
Embedded computer systems. Embedded computer systems--Design and construction.