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010			_a 2011377174
040			_aUKM _beng _cUKM _dUMC _dVRC _dUBC _dDEBBG _dOCL _dDLC _dBDX _dHDC _dUKMGB _dOCLCF
020			_a9780470127421 (pbk.)
020			_a0470127422 (pbk.)
035			_a(OCoLC)190776332
042			_aukblcatcopy
050		4	_aTK7874.75 _b.X55 2008
082	0	4	_a621.395 _222
100	1		_aXiu, Liming.
245	1	0	_aVLSI circuit design methodology demystified : _ba conceptual taxonomy / _cLiming Xiu.
260			_aHoboken, N.J. : _bWiley ; _a[Chichester : _bJohn Wiley, distributor], _cc2008.
300			_axvii, 202 p. : _bill. ; _c24 cm.
504			_aIncludes bibliographical references and index.
520			_aThis book was written to arm engineers qualified and knowledgeable in the area of VLSI circuits with the essential knowledge they need to get into this exciting field and to help those already in it achieve a higher level of proficiency. _bThis book was written to arm engineers qualified and knowledgeable in the area of VLSI circuits with the essential knowledge they need to get into this exciting field and to help those already in it achieve a higher level of proficiency. Few people truly understand how a large chip is developed, but an understanding of the whole process is necessary to appreciate the importance of each part of it and to understand the process from concept to silicon. It will teach readers how to become better engineers through a practical approach of diagnosing and attacking real-world problems.
505	0	0	_gChapter 1 _tThe Big Picture _g1 -- _g1 _tWhat is a chip? _g1 -- _g2 _tWhat are the requirements of a successful chip design? _g3 -- _g3 _tWhat are the challenges in today's very deep submicron (VDSM), multimillion gate designs? _g4 -- _g4 _tWhat major process technologies are used in today's design environment? _g5 -- _g5 _tWhat are the goals of new chip design? _g8 -- _g6 _tWhat are the major approaches of today's very large scale integration (VLSI) circuit design practices? _g9 -- _g7 _tWhat is standard cell-based, application-specific integrated circuit (ASIC) design methodology? _g11 -- _g8 _tWhat is the system-on-chip (SoC) approach? _g12 -- _g9 _tWhat are the driving forces behind the SoC trend? _g15 -- _g10 _tWhat are the major tasks in developing a SoC chip from concept to silicon? _g15 -- _g11 _tWhat are the major costs of developing a chip? _g16 -- _gChapter 2 _tThe Basics of the CMOS Process and Devices _g17 -- _g12 _tWhat are the major process steps in building MOSFET transistors? _g17 -- _g13 _tWhat are the two types of MOSFET transistors? _g19 -- _g14 _tWhat are base layers and metal layers? _g20 -- _g15 _tWhat are wafers and dies? _g24 -- _g16 _tWhat is semiconductor lithography? _g28 -- _g17 _tWhat is a package? _g33 -- _gChapter 3 _tThe Challenges in VLSI Circuit Design _g41 -- _g18 _tWhat is the role of functional verification in the IC design process? _g41 -- _g19 _tWhat are some of the design integrity issues? _g44 -- _g20 _tWhat is design for testability? _g46 -- _g21 _tWhy is reducing the chip's power consumption so important? _g48 -- _g22 _tWhat are some of the challenges in chip packaging? _g49 -- _g23 _tWhat are the advantages of design reuse? _g50 -- _g24 _tWhat is hardware/software co-design? _g51 -- _g25 _tWhy is the clock so important? _g54 -- _g26 _tWhat is the leakage current problem? _g57 -- _g27 _tWhat is design for manufacturability? _g60 -- _g28 _tWhat is chip reliability? _g62 -- _g29 _tWhat is analog integration in the digital environment? _g65 -- _g30 _tWhat is the role of EDA tools in IC design? _g67 -- _g31 _tWhat is the role of the embedded processor in the SoC environment? _g69 -- _gChapter 4 _tCell-Based ASIC Design Methodology _g73 -- _g32 _tWhat are the major tasks and personnel required in a chip design project? _g73 -- _g33 _tWhat are the major steps in ASIC chip construction? _g74 -- _g34 _tWhat is the ASIC design flow? _g75 -- _g35 _tWhat are the two major aspects of ASIC design flow? _g77 -- _g36 _tWhat are the characteristics of good design flow? _g80 -- _g37 _tWhat is the role of market research in an ASIC project? _g81 -- _g38 _tWhat is the optimal solution of an ASIC project? _g82 -- _g39 _tWhat is system-level study of a project? _g84 -- _g40 _tWhat are the approaches for verifying design at the system level? _g85 -- _g41 _tWhat is register-transfer-level (RTL) system-level description? _g86 -- _g42 _tWhat are methods of verifying design at the register-transfer-level? _g87 -- _g43 _tWhat is a test bench? _g88 -- _g44 _tWhat is code coverage? _g89 -- _g45 _tWhat is functional coverage? _g89 -- _g46 _tWhat is bug rate convergence? _g90 -- _g47 _tWhat is design planning? _g91 -- _g48 _tWhat are hard macro and soft macro? _g92 -- _g49 _tWhat is hardware description language (HDL)? _g92 -- _g50 _tWhat is register-transfer-level (RTL) description of hardware? _g93 -- _g51 _tWhat is standard cell? What are the differences among standard cell, gate-array, and sea-of-gate approaches? _g94 -- _g52 _tWhat is an ASIC library? _g103 -- _g53 _tWhat is logic synthesis? _g105 -- _g54 _tWhat are the optimization targets of logic synthesis? _g106 -- _g55 _tWhat is schematic or netlist? _g107 -- _g56 _tWhat is the gate count of a design? _g111 -- _g57 _tWhat is the purpose of test insertion during logic synthesis? _g111 -- _g58 _tWhat is the most commonly used model in VLSI circuit testing? _g112 -- _g59 _tWhat are controllability and observability in a digital circuit? _g114 -- _g60 _tWhat is a testable circuit? _g115 -- _g61 _tWhat is the aim of scan insertion? _g116 -- _g62 _tWhat is fault coverage? What is defect part per million (DPPM)? _g117 -- _g63 _tWhy is design for testability important for a product's financial success? _g119 -- _g64 _tWhat is chip power usage analysis? _g120 -- _g65 _tWhat are the major components of CMOS power consumption? _g121 -- _g66 _tWhat is power optimization? _g123 -- _g67 _tWhat is VLSI physical design? _g123 -- _g68 _tWhat are the problems that make VLSI physical design so challenging? _g124 -- _g69 _tWhat is floorplanning? _g128 -- _g70 _tWhat is the placement process? _g131 -- _g71 _tWhat is the routing process? _g133 -- _g72 _tWhat is a power network? _g135 -- _g73 _tWhat is clock distribution? _g139 -- _g74 _tWhat are the key requirements for constructing a clock tree? _g143 -- _g75 _tWhat is the difference between time skew and length skew in a clock tree? _g145 -- _g76 _tWhat is scan chain? _g149 -- _g77 _tWhat is scan chain reordering? _g151 -- _g78 _tWhat is parasitic extraction? _g152 -- _g79 _tWhat is delay calculation? _g155 -- _g80 _tWhat is back annotation? _g156 -- _g81 _tWhat kind of signal integrity problems do place and route tools handle? _g156 -- _g82 _tWhat is cross-talk delay? _g157 -- _g83 _tWhat is cross-talk noise? _g158 -- _g84 _tWhat is IR drop? _g159 -- _g85 _tWhat are the major netlist formats for design representation? _g162 -- _g86 _tWhat is gate-level logic verification before tapeout? _g162 -- _g87 _tWhat is equivalence check? _g163 -- _g88 _tWhat is timing verification? _g164 -- _g89 _tWhat is design constraint? _g165 -- _g90 _tWhat is static timing analysis (STA)? _g165 -- _g91 _tWhat is simulation approach on timing verification _g169 -- _g92 _tWhat is the logical-effort-based timing closure approach? _g173 -- _g93 _tWhat is physical verification? _g178 -- _g94 _tWhat are design rule check (DRC), design verification (DV), and geometry verification (GV)? _g179 -- _g95 _tWhat is schematic verification (SV) or layout versus schematic (LVS)? _g181 -- _g96 _tWhat is automatic test pattern generation (ATPG)? _g182 -- _g97 _tWhat is tapeout? _g184 -- _g98 _tWhat is yield? _g184 -- _g99 _tWhat are the qualities of a good IC implementation designed? _g187.
650		0	_aIntegrated circuits _xVery large scale integration.
650		0	_aIntegrated circuits _xDesign.
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