000			12056cam a2200373Ia 4500
001			u8393
003			SA-PMU
005			20210418123156.0
008			050628s2005 ne a b 001 0 eng d
010			_a 2005299338
040			_aPIT _beng _cPIT _dOCLCQ _dDLC _dBAKER _dLVB _dYDXCP _dBTCTA _dNLGGC _dOCLCG _dBDX _dHDC _dSGB _dOCLCF
020			_a0127518037
020			_a9780127518039
035			_a(OCoLC)60756339
050	0	0	_aTK7874.58 _b.W55 2005
082	0	0	_a621.3815/48 _222
100	1		_aWile, Bruce.
245	1	0	_aComprehensive functional verification the complete industry cycle / _cBruce Wile, John C. Goss, Wolfgang Roesner.
260			_aAmsterdam ; _aBoston : _bElsevier/Morgan Kaufmann, _cc2005.
300			_axiii, 676 p. : _bill. ; _c24 cm.
504			_aIncludes bibliographical references (p. 657-662) and index.
505	0	0	_gPart I _tIntroduction to Verification -- _g1 _tVerification in the Chip Design Process _g5 -- _g1.1 _tIntroduction to Functional Verification _g5 -- _g1.2 _tThe Verification Challenge _g8 -- _g1.2.1 _tThe Challenge of State Space Explosion _g9 -- _g1.2.2 _tThe Challenge of Detecting Incorrect Behavior _g12 -- _g1.3 _tMission and Goals of Verification _g14 -- _g1.3.1 _tVerification Engineer "Musts" _g18 -- _g1.4 _tCost of Verification _g20 -- _g1.4.1 _tEngineering Costs and the Need for an Independent Verification Team _g20 -- _g1.4.2 _tDesign Automation Tools _g21 -- _g1.4.3 _tTime _g22 -- _g1.5 _tAreas of Verification Beyond the Scope of this Book _g23 -- _g1.6 _tThe Verification Cycle: A Structured Process _g24 -- _g1.6.1 _tFunctional Specification _g25 -- _g1.6.2 _tCreate Verification Plan _g26 -- _g1.6.3 _tDevelop Environment _g27 -- _g1.6.4 _tDebug HDL and Environment _g27 -- _g1.6.5 _tRegression _g28 -- _g1.6.6 _tFabricate Hardware _g28 -- _g1.6.7 _tDebug Fabricated Hardware (Systems Test) _g29 -- _g1.6.8 _tEscape Analysis _g29 -- _g1.6.9 _tCommon Verification Cycle Breakdowns _g30 -- _g2 _tVerification Flow _g35 -- _g2.1 _tVerification Hierarchy _g35 -- _g2.1.1 _tLevels of Verification _g36 -- _g2.1.2 _tWhat Level to Choose? _g41 -- _g2.2 _tStrategy of Verification _g45 -- _g2.2.1 _tDriving Principles _g45 -- _g2.2.2 _tChecking Strategies _g50 -- _g2.2.3 _tChecking the Black Box _g55 -- _g2.2.5 _tThe General Simulation Environment _g61 -- _g2.2.6 _tVerification Methodology Evolution _g62 -- _g3 _tFundamentals of Simulation Based Verification _g73 -- _g3.1 _tBasic Verification Environment: A Test Bench _g73 -- _g3.1.1 _tStimulus Component _g74 -- _g3.1.2 _tMonitor _g80 -- _g3.1.3 _tChecker _g82 -- _g3.1.4 _tScoreboard _g83 -- _g3.1.5 _tDesign Under Verification _g85 -- _g3.2 _tObservation Points: Black-Box, White-Box and Grey-Box Verification _g86 -- _g3.2.1 _tBlack Box _g86 -- _g3.2.2 _tWhite Box _g87 -- _g3.2.3 _tGrey Box _g88 -- _g3.3 _tAssertion Based Verification-An Overview _g89 -- _g3.3.1 _tThe Importance of Assertions _g90 -- _g3.3.2 _tAssertions Express Design Intent _g92 -- _g3.3.3 _tClassification of Assertions _g94 -- _g3.4 _tTest Benches and Testing Strategies _g95 -- _g3.4.1 _tDeterministic Test Benches _g95 -- _g3.4.2 _tSelf-Checking Test Benches _g97 -- _g4 _tThe Verification Plan _g103 -- _g4.1 _tThe Functional Specification _g103 -- _g4.2 _tThe Evolution of the Verification Plan _g104 -- _g4.3 _tContents of the Verification Plan _g106 -- _g4.3.1 _tDescription of Verification Levels _g106 -- _g4.3.2 _tRequired Tools _g107 -- _g4.3.3 _tRisks and Dependencies _g108 -- _g4.3.4 _tFunctions to be Verified _g109 -- _g4.3.5 _tSpecific Tests and Methods: Environment _g111 -- _g4.3.6 _tCoverage Requirements _g115 -- _g4.3.7 _tTest Case Scenarios: Matrix _g116 -- _g4.3.8 _tResource Requirements _g117 -- _g4.3.9 _tSchedule Details _g118 -- _g4.4 _tVerification Example: Calc1 _g121 -- _g4.4.1 _tDesign Description _g121 -- _g4.4.2 _tCreating the Verification Plan for Calc1 _g125 -- _g4.4.3 _tDeterministic Verification of Calc1 _g131 -- _gPart II _tSimulation Based Verification -- _g5 _tHDLs and Simulation Engines _g141 -- _g5.1 _tHardware Description Languages _g143 -- _g5.1.1 _tHDL Modeling Levels _g143 -- _g5.1.2 _tVerification Aspects of HDLs _g153 -- _g5.2 _tSimulation Engines: Introduction _g159 -- _g5.2.1 _tSpeed versus Accuracy _g160 -- _g5.2.2 _tMaking the Right Methodology Choices _g162 -- _g5.3 _tEvent-Driven Simulation _g162 -- _g5.3.1 _tHierarchical Model Network _g163 -- _g5.3.2 _tModel Evaluation Over Time _g165 -- _g5.3.3 _tEvent-Driven Control of Model Evaluation _g167 -- _g5.3.4 _tImplementation Sketch of an Event-Driven Simulation Engine _g172 -- _g5.4 _tImproving Simulation Throughput _g178 -- _g5.5 _tCycle-Based Simulation _g182 -- _g5.5.1 _tSynchronous Design _g183 -- _g5.5.2 _tThe Cycle-Based Simulation Algorithm _g184 -- _g5.5.3 _tExtensions to Basic Cycle-Based Simulation Engines _g188 -- _g5.6 _tWaveform Viewers _g191 -- _g6 _tCreating Environments _g199 -- _g6.1 _tTest Bench Writing Tools _g200 -- _g6.1.1 _tHDL Languages as Test Bench Tool _g201 -- _g6.1.2 _tC/C++ Libraries _g207 -- _g6.1.3 _tHigh-Level Verification Languages _g230 -- _g6.1.4 _tOther Test Bench Tools _g241 -- _g6.2 _tVerification Coverage _g243 -- _g6.2.2 _tFunctional Verification Test Coverage versus Manufacturing Test Coverage _g246 -- _g6.2.3 _tStructural Coverage _g247 -- _g6.2.4 _tFunctional Coverage _g251 -- _g6.2.5 _tCoverage Bulk Data Collection and Management _g254 -- _g6.2.6 _tThe Right Coverage Analysis Strategy _g255 -- _g7 _tStrategies for Simulation-Based Stimulus Generation _g259 -- _g7.1 _tCalc2 Overview _g260 -- _g7.1.1 _tCalc2 Verification Plan _g263 -- _g7.1.2 _tCalc2 and the Strategies for Stimulus Generation _g269 -- _g7.2 _tStrategies for Stimulus Generation _g270 -- _g7.2.1 _tTypes of Stimulus Generation _g270 -- _g7.2.2 _tGeneral Algorithms for Stimulus Components _g275 -- _g7.2.3 _tApplying the Four Types of Stimulus Generation to Calc2 _g277 -- _g7.2.4 _tSeeding Random Test Cases _g294 -- _g7.2.5 _tConstraint Solving in Random Environments _g297 -- _g7.2.6 _tCoverage Techniques in Random Environments _g301 -- _g7.2.7 _tMaking Rare Events Occur _g303 -- _g7.2.8 _tStimulus Generation of Deadlocks and Livelocks _g306 -- _g8 _tStrategies for Results Checking in Simulation-Based Verification _g313 -- _g8.1 _tTypes of Result Checking _g313 -- _g8.1.1 _tOn-the-Fly Checking versus End-of-Test Case Checking _g314 -- _g8.1.2 _tPregenerated Test Cases versus On-the-Fly Generated Test Cases _g321 -- _g8.1.3 _tApplying the Checking Strategies to Calc2 _g322 -- _g8.2 _tDebug _g334 -- _g8.2.1 _tDebug Process _g336 -- _g8.2.2 _tHow Different Types of Test Benches Affect Debug _g349 -- _g9 _tPervasive Function Verification _g355 -- _g9.1 _tSystem Reset and Bring-Up _g356 -- _g9.1.1 _tReset Line Initialization _g357 -- _g9.1.2 _tScan Initialization _g361 -- _g9.1.3 _tTestability and Built-In Self-Test _g363 -- _g9.2 _tError and Degraded Mode Handling _g368 -- _g9.2.1 _tVerifying Error Detection _g368 -- _g9.2.2 _tVerifying Self-Healing Hardware _g372 -- _g9.3 _tVerifying Hardware Debug Assists _g380 -- _g9.3.1 _tVerifying Scan Ring Dumps _g381 -- _tLow Power Mode Verification _g384 -- _g9.4.1 _tPower Savings Through Disabling Functional Units _g385 -- _g9.4.2 _tPower Savings Through Cycle Time Degradation _g387 -- _g10 _tRe-Use Strategies and System Simulation _g391 -- _g10.1 _tRe-Use Strategies _g392 -- _g10.1.1 _tGuidelines for Re-Use _g395 -- _g10.1.2 _tHorizontal Re-Use _g403 -- _g10.1.3 _tVertical Re-Use _g404 -- _g10.1.4 _tApplying Re-Use to Calc2 _g405 -- _g10.1.5 _tAssertion Re-Use _g410 -- _g10.2 _tSystem Simulation _g412 -- _g10.2.1 _tSystem Test Bench _g412 -- _g10.2.2 _tConnectivity and Interaction of Units _g414 -- _g10.2.3 _tVerification Challenges in a Re-Usable IP World _g418 -- _g10.3 _tBeyond General-Purpose Logic Simulation _g420 -- _g10.3.1 _tAcceleration _g421 -- _g10.3.2 _tEmulation _g427 -- _g10.3.3 _tHardware/Software Co-verification _g428 -- _g10.3.4 _tCo-simulation _g430 -- _gPart III _tFormal Verification -- _g11 _tIntroduction to Formal Verification _g439 -- _g11.1.1 _tDesign Correctness and Specifications _g441 -- _g11.1.2 _tComputational Complexity _g443 -- _g11.1.3 _tThe Myth of Linear Scaling of Simulation _g445 -- _g11.1.4 _tMathematical Proof Methods in Formal Verification _g446 -- _g11.2 _tFormal Boolean Equivalence Checking _g448 -- _g11.2.1 _tThe Role of Equivalence Checking in the VLSI Design Flow _g449 -- _g11.2.2 _tMain Elements of an Equivalence Checker Tool _g450 -- _g11.2.3 _tSequential and Combinational Boolean Equivalence Checking _g451 -- _g11.2.4 _tCore Algorithms for Combinational Equivalence Checking _g454 -- _g11.2.5 _tBlueprint of a Modern Equivalence Checking Tool _g465 -- _g11.3 _tFunctional Formal Verification-Property Checking _g467 -- _g11.3.1 _tProperty Checking vs.
505	0	0	_tSequential Equivalence Checking _g468 -- _g11.3.2 _tThe Myth of Complete Verification with FV _g470 -- _g11.3.3 _tProperties for an Example Design _g471 -- _g11.3.4 _tDUV Drivers for Formal Verification _g476 -- _g11.3.5 _tState Space Traversal and Temporal Logic _g479 -- _g11.3.6 _tFunctional Formal Verification Tool Flow _g483 -- _g12 _tUsing Formal Verification _g487 -- _g12.1 _tProperty Specification Using an HDL Library _g488 -- _g12.1.1 _tThe Open Verification Library (OVL) _g489 -- _g12.1.2 _tUsing OVL to Specify Properties _g495 -- _g12.2 _tThe Property Specification Language PSL _g499 -- _g12.2.2 _tThe Boolean Layer of PSL _g501 -- _g12.2.3 _tThe Temporal Layer of PSL _g504 -- _g12.2.4 _tThe Verification Layer of PSL _g508 -- _g12.2.5 _tThe Modeling Layer of PSL _g511 -- _g12.2.6 _tUsing PSL to Specify Properties _g512 -- _g12.2.7 _tAdvanced PSL Topics and Caveats _g514 -- _g12.3 _tProperty Checking Using Formal Verification _g521 -- _g12.3.1 _tProperty Re-Use between Simulation and FV _g521 -- _g12.3.2 _tModel Compliation _g522 -- _g12.3.3 _tFormal Functional Verification Algorithms _g523 -- _g12.3.4 _tSolutions to Address the Problem of State Space Explosion _g527 -- _g12.3.5 _tSemi-Formal Verification _g530 -- _g12.3.6 _tEDA Vendors Supplying Formal and Semi-Formal Verification Tools _g532 -- _gPart IV _tComprehensive Verification -- _g13 _tCompleting the Verification Cycle _g539 -- _g13.1 _tRegression _g540 -- _g13.1.1 _tRegression in the Verification Flow _g540 -- _g13.1.2 _tRegression Quality _g542 -- _g13.1.3 _tRegression Efficiency _g543 -- _g13.2 _tProblem Tracking _g548 -- _g13.3 _tTape-Out Readiness _g552 -- _g13.3.1 _tMetrics _g552 -- _g13.3.2 _tCompletion Criteria _g557 -- _g13.4 _tEscape Analysis _g559 -- _g13.4.1 _tIndividual Bug Analysis _g561 -- _g13.4.2 _tEscape Examples _g569 -- _g13.4.3 _tEscape Analysis Trends _g572 -- _g14 _tAdvanced Verification Techniques _g579 -- _g14.1 _tSave Verification Cycles-Bootstrapping the Verification Process _g580 -- _g14.1.1 _tSeparating POR and Mainline Verification _g580 -- _g14.1.2 _tBootstrapping the DUV into High-Potential States _g583 -- _g14.1.3 _tManipulating the DUV Specification Provoking States of Resource Conflict _g585 -- _g14.2 _tHigh-Level Modeling-Concepts _g586 -- _g14.2.1 _tApplications of the High-Level Model _g587 -- _g14.2.2 _tHigh-Level Modeling Styles _g590 -- _g14.3 _tCoverage-Directed Generation _g595 -- _g15.1 _tThe Line Delete Escape _g603 -- _g15.1.1 _tThe Background _g603 -- _g15.1.2 _tThe Verification Environments _g605 -- _g15.1.3 _tThe Escape _g607 -- _g15.2 _tBranch History Table _g608
520			_aA key strength of this book is that it describes the entire verification cycle and details each stage. The organization of the book follows the cycle, demonstrating how functional verification engages all aspects of the overall design effort and how individual cycle stages relate to the larger design process. Throughout the text, the authors leverage their 35 plus years experience in functional verification, providing examples and case studies, and focusing on the skills, methods, and tools needed to complete each verification task. Additionally, the major vendors (Mentor Graphics, Cadence Design Systems, Verisity, and Synopsys) have implemented key examples from the text and made these available on line, so that the reader can test out the methods described in the text.
650		0	_aIntegrated circuits _xVerification.
650		0	_aComputer engineering.
700	1		_aGoss, John C.
700	1		_aRoesner, W. _q(Wolfgang)
856	4	2	_3Publisher description _uhttp://catdir.loc.gov/catdir/enhancements/fy0627/2005299338-d.html
856	4	1	_3Table of contents _uhttp://catdir.loc.gov/catdir/enhancements/fy0627/2005299338-t.html
942			_cBOOK
994			_aZ0 _bSUPMU
596			_a1 2
999			_c1915 _d1915