000			11372cam a22003737a 4500
001			u8408
003			SA-PMU
005			20210418123258.0
008			070419s2006 caua 001 0 eng d
010			_a 2007296561
040			_aUIU _beng _cUIU _dDLC _dYDXCP _dBAKER _dLML _dBTCTA _dAU@ _dUKM _dMIA _dCUY _dHDC _dGPM _dLVB _dCUD _dSZ9XM _dOCLCO _dOCLCF
020			_a0123695260
020			_a9780123695260
035			_a(OCoLC)72535240 _z(OCoLC)69733202 _z(OCoLC)84843363
042			_alccopycat
050	0	0	_aTK7895.E42 _bC88 2007
082	0	4	_a621.392 _222
245	0	0	_aCustomizable embedded processors : _bdesign technologies and applications / _cPaolo Ienne and Rainer Leupers [editors].
260			_aSan Francisco, Calif. : _bMorgan Kaufmann ; _aOxford : _bElsevier Science [distributor], _c2006.
300			_axxviii, 497 p. : _bill. ; _c25 cm.
490	1		_aMorgan Kaufmann series in systems on silicon
504			_aIncludes bibliographical references (p. [465]-484) and index.
505	0	0	_tIn Praise of Customizable Embedded Processors _gi -- _gPart I _tOpportunities and Challenges -- _g1 _tFrom Pret-a-Porter to Tailor-Made / _rPaolo Ienne, Rainer Leupers _g3 -- _g1.1 _tThe Call for Flexibility _g4 -- _g1.2 _tCool Chips for Shallow Pockets _g5 -- _g1.3 _tA Million Processors for the Price of One? _g5 -- _g1.4 _tProcessors Coming of Age _g7 -- _g1.6 _tTravel Broadens the Mind _g9 -- _g2 _tOpportunities for Application-Specific Processors: The Case of Wireless Communications / _rGerd Ascheid, Heinrich Meyr _g11 -- _g2.1 _tFuture Mobile Communication Systems _g12 -- _g2.2 _tHeterogeneous MPSoC for Digital Receivers _g14 -- _g2.2.1 _tThe Fundamental Tradeoff between Energy Efficiency and Flexibility _g14 -- _g2.2.2 _tHow to Exploit the Huge Design Space? _g17 -- _g2.2.3 _tCanonical Receiver Structure _g19 -- _g2.2.4 _tAnalyzing and Classifying the Functions of a Digital Receiver _g21 -- _g2.2.5 _tExploiting Parallelism _g25 -- _g2.3 _tASIP Design _g26 -- _g2.3.1 _tProcessor Design Flow _g26 -- _g2.3.2 _tArchitecture Description Language Based Design _g28 -- _g2.3.3 _tToo Much Automation Is Bad _g29 -- _g2.3.4 _tProcessor Design: The LISATek Approach _g30 -- _g2.3.5 _tDesign Competence Rules the World _g33 -- _g2.3.6 _tApplication-Specific or Domain-Specific Processors? _g35 -- _g3 _tCustomizing Processors: Lofty Ambitions, Stark Realities / _rJoseph A. Fisher, Paolo Faraboschi, Cliff Young _g39 -- _g3.1 _tThe "CFP" project at HP Labs _g41 -- _g3.2 _tSearching for the Best Architecture Is Not a Machine-Only Endeavor _g45 -- _g3.3 _tDesigning a CPU Core Still Takes a Very Long Time _g46 -- _g3.4 _tDon't Underestimate Competitive Technologies _g48 -- _g3.5 _tSoftware Developers Don't Always Help You _g49 -- _g3.6 _tThe Embedded World Is Not Immune to Legacy Problems _g51 -- _g3.7 _tCustomization Can Be Trouble _g52 -- _gPart II _tAspects of Processor Customization -- _g4 _tArchitecture Description Languages / _rPrabhat Mishra, Nikil Dutt _g59 -- _g4.1 _tADLs and other languages _g60 -- _g4.2 _tSurvey of Contemporary ADLs _g62 -- _g4.2.1 _tContent-Oriented Classification of ADLs _g62 -- _g4.2.2 _tObjective-Based Classification of ADLs _g72 -- _g5 _tC Compiler Retargeting / _rRainer Leupers _g77 -- _g5.1 _tCompiler Construction Background _g79 -- _g5.1.1 _tSource Language Frontend _g79 -- _g5.1.2 _tIntermediate Representation and Optimization _g80 -- _g5.1.3 _tMachine Code Generation _g83 -- _g5.2 _tApproaches to Retargetable Compilation _g91 -- _g5.2.1 _tMIMOLA _g92 -- _g5.2.2 _tGNU C Compiler _g94 -- _g5.2.3 _tLittle C Compiler _g94 -- _g5.2.4 _tCoSy _g95 -- _g5.3 _tProcessor Architecture Exploration _g98 -- _g5.3.1 _tMethodology and Tools for ASIP Design _g98 -- _g5.3.2 _tADL-Based Approach _g100 -- _g5.4 _tC Compiler Retargeting in the LISATek Platform _g104 -- _g5.4.2 _tRegister Allocator and Scheduler _g105 -- _g5.4.3 _tCode Selector _g107 -- _g5.4.4 _tResults _g111 -- _g6 _tAutomated Processor Configuration and Instruction Extension / _rDavid Goodwin, Steve Leibson, Grant Martin _g117 -- _g6.1 _tAutomation Is Essential for ASIP Proliferation _g118 -- _g6.2 _tThe Tensilica Xtensa LX Configurable Processor _g119 -- _g6.3 _tGenerating ASIPs Using Xtensa _g121 -- _g6.4 _tAutomatic Generation of ASIP Specifications _g123 -- _g6.5 _tCoding an Application for Automatic ASIP Generation _g125 -- _g6.6 _tXPRES Benchmarking Results _g126 -- _g6.7 _tTechniques for ASIP Generation _g128 -- _g6.7.1 _tReference Examples for Evaluating XPRES _g128 -- _g6.7.2 _tVLIW-FLIX: Exploiting Instruction Parallelism _g129 -- _g6.7.3 _tSIMD (Vectorization): Exploiting Data Parallelism _g131 -- _g6.7.4 _tOperator Fusion: Exploiting Pipeline Parallelism _g133 -- _g6.7.5 _tCombining Techniques _g134 -- _g6.8 _tExploring the Design Space _g136 -- _g6.9 _tEvaluating Xpres Estimation Methods _g137 -- _g6.9.1 _tApplication Performance Estimation _g139 -- _g6.9.2 _tASIP Area Estimation _g139 -- _g6.9.3 _tCharacterization Benchmarks _g140 -- _g6.9.4 _tPerformance and Area Estimation _g141 -- _g7 _tAutomatic Instruction-Set Extensions / _rLaura Pozzi, Paolo Ienne _g145 -- _g7.1 _tBeyond Traditional Compilers _g144 -- _g7.1.1 _tStructure of the Chapter _g147 -- _g7.2 _tBuilding Block for Instruction Set Extension _g147 -- _g7.2.1 _tMotivation _g148 -- _g7.2.2 _tProblem Statement: Identification and Selection _g148 -- _g7.2.3 _tIdentification Algorithm _g152 -- _g7.2.4 _tResults _g155 -- _g7.3 _tHeuristics _g160 -- _g7.3.1 _tMotivation _g160 -- _g7.3.2 _tTypes of Heuristic Algorithms _g161 -- _g7.3.3 _tA Partitioning-Based Heuristic Algorithm _g162 -- _g7.3.4 _tA Clustering Heuristic Algorithm _g162 -- _g7.4 _tState-Holding Instruction-Set Extensions _g163 -- _g7.4.1 _tMotivation _g164 -- _g7.4.2 _tLocal-Memory Identification Algorithm _g165 -- _g7.4.3 _tResults _g167 -- _g7.5 _tExploiting Pipelining to Relax I/O Constraints _g170 -- _g7.5.1 _tMotivation _g171 -- _g7.5.2 _tReuse of the Basic Identification Algorithm _g173 -- _g7.5.3 _tProblem Statement: Pipelining _g174 -- _g7.5.4 _tI/O Constrained Scheduling Algorithm _g176 -- _g7.5.5 _tResults _g177 -- _g8 _tChallenges to Automatic Customization / _rNigel Topham _g185 -- _g8.1 _tThe ARCompact Instruction Set Architecture _g186 -- _g8.1.1 _tMechanisms for Architecture Extension _g190 -- _g8.1.2 _tARCompact Implementations _g190 -- _g8.2 _tMicroarchitecture Challenges _g191 -- _g8.3 _tCase Study-Entropy Decoding _g193 -- _g8.3.1 _tCustomizing VLD Extensions _g195 -- _g8.4 _tLimitations of Automated Extension _g203 -- _g8.5 _tThe Benefits of Architecture Extension _g205 -- _g8.5.1 _tCustomization Enables CoDesign _g205 -- _g8.5.2 _tCustomization Offers Performance Headroom _g206 -- _g8.5.3 _tCustomization Enables Platform IP _g206 -- _g8.5.4 _tCustomization Enables Differentiation _g207 -- _g9 _tCoprocessor Generation from Executable Code / _rRichard Taylor, David Stewart _g209 -- _g9.2 _tUser Level Flow _g210 -- _g9.3 _tIntegration with Embedded Software _g214 -- _g9.4 _tCoprocessor Architecture _g215 -- _g9.5 _tILP Extraction Challenges _g218 -- _g9.6 _tInternal Tool Flow _g220 -- _g9.7 _tCode Mapping Approach _g225 -- _g9.8 _tSynthesizing Coprocessor Architectures _g228 -- _g9.9 _tA Real-World Example _g229 -- _g10 _tDatapath Synthesis / _rPhilip Brisk, Majid Sarrafzadeh _g233 -- _g10.2 _tCustom Instruction Selection _g234 -- _g10.3 _tTheoretical Preliminaries _g236 -- _g10.3.1 _tThe Minimum Area-Cost Acyclic Common Supergraph Problem _g236 -- _g10.3.2 _tSubsequence and Substring Matching Techniques _g237 -- _g10.4 _tMinimum Area-Cost Acyclic Common Supergraph Heuristic _g238 -- _g10.4.1 _tPath-Based Resource Sharing _g238 -- _g10.4.3 _tPseudocode _g240 -- _g10.5 _tMultiplexer Insertion _g246 -- _g10.5.1 _tUnary and Binary Noncommutative Operators _g246 -- _g10.5.2 _tBinary Commutative Operators _g247 -- _g10.6 _tDatapath Synthesis _g249 -- _g10.6.1 _tPipelined Datapath Synthesis _g249 -- _g10.6.2 _tHigh-Level Synthesis _g249 -- _g10.7 _tExperimental Results _g250 -- _g11 _tInstruction Matching and Modeling / _rSri Parameswaran, Jorg Henkel, Newton Cheung _g257 -- _g11.1 _tMatching Instructions _g259 -- _g11.1.1 _tIntroduction to Binary Decision Diagrams _g259 -- _g11.1.2 _tThe Translator _g261 -- _g11.1.3 _tFiltering Algorithm _g264 -- _g11.1.4 _tCombinational Equivalence Checking Model _g265 -- _g11.1.5 _tResults _g265 -- _g11.2 _tModeling _g268 -- _g11.2.2 _tCustomization Parameters _g270 -- _g11.2.3 _tCharacterization for Various Constraints _g271 -- _g11.2.4 _tEquations for Estimating Area, Latency, and Power Consumption _g273 -- _g11.2.5 _tEvaluation Results _g274 -- _g12 _tProcessor Verification / _rDaniel Grosse, Robert Siegmund, Rolf Drechsler _g281 -- _g12.1 _tMotivation _g281 -- _g12.2 _tOverview of Verification Approaches _g282 -- _g12.2.1 _tSimulation _g282 -- _g12.2.2 _tSemiformal Techniques _g284 -- _g12.2.3 _tProof Techniques _g284 -- _g12.2.4 _tCoverage _g285 -- _g12.3 _tFormal Verification of a RISC CPU _g285 -- _g12.3.1 _tVerification Approach _g286 -- _g12.3.2 _tSpecification _g287 -- _g12.3.3 _tSystemC Model _g288 -- _g12.3.4 _tFormal Verification _g289 -- _g12.4 _tVerification Challenges in Customizable and Configurable Embedded Processors _g293 -- _g12.5 _tVerification of Processor Peripherals _g294 -- _g12.5.1 _tCoverage-Driven Verification Based on Constrained-Random Stimulation _g294 -- _g12.5.2 _tAssertion-Based Verification of Corner Cases _g297 -- _g12.5.3 _tCase Study: Verification of an On-Chip Bus Bridge _g298 -- _g13 _tSub-RISC Processors / _rAndrew Mihal, Scott Weber, Kurt Keutzer _g303 -- _g13.1 _tConcurrent Architectures, Concurrent Applications _g303 -- _g13.2 _tMotivating Sub-RISC PEs _g306 -- _g13.2.1 _tRISC PEs _g307 -- _g13.2.2 _tCustomizable Datapaths _g311 -- _g13.2.3 _tSynthesis Approaches _g311 -- _g13.2.4 _tArchitecture Description Languages _g311 -- _g13.3 _tDesigning TIPI Processing Elements _g316 -- _g13.3.1 _tBuilding Datapath Models _g317 -- _g13.3.2 _tOperation
505	0	0	_tExtraction _g318 -- _g13.3.3 _tSingle PE Simulator Generation _g318 -- _g13.3.4 _tTIPI Multiprocessors _g319 -- _g13.3.5 _tMultiprocessor Simulation and RTL Code Generation _g321 -- _g13.4 _tDeploying Applications with Cairn _g321 -- _g13.4.1 _tThe Cairn Application Abstraction _g323 -- _g13.4.2 _tModel Transforms _g325 -- _g13.4.3 _tMapping Models _g325 -- _g13.4.4 _tCode Generation _g326 -- _g13.5 _tIPv4 Forwarding Design Example _g327 -- _g13.5.1 _tDesigning a PE for Click _g327 -- _g13.5.2 _tClickPE Architecture _g328 -- _g13.5.3 _tClickPE Control Logic _g329 -- _g13.5.4 _tLuleaPE Architecture _g330 -- _g13.6 _tPerformance Results _g331 -- _g13.6.1 _tClickPE Performance _g332 -- _g13.6.2 _tLuleaPE Performance _g333 -- _g13.6.3 _tPerformance Comparison _g334 -- _g13.6.4 _tPotentials for Improvement _g335 -- _g14 _tApplication Specific Instruction Set Processor for UMTS-FDD Cell Search / _rKimmo Puusaari, Timo Yli-Pietila, Kim Rounioja _g339 -- _g14.1 _tASIP on Wireless Modem Design _g340 -- _g14.1.1 _tThe Role of ASIP _g340 -- _g14.1.2 _tASIP Challenges for a System House _g343 -- _g14.1.3 _tPotential ASIP Use Cases in Wireless Receivers _g344 -- _g14.2 _tFunctionality of Cell Search ASIP _g346 -- _g14.2.1 _tCell Search-Related Channels and Codes _g346 -- _g14.2.2 _tCell Search Functions _g347 -- _g14.2.3 _tRequirements for the ASIP _g347 -- _g14.3 _tCell Search ASIP Design and Verification _g348 -- _g14.3.1 _tMicroarchitecture _g348 -- _g14.3.2 _tSpecial Function Units _g350 -- _g14.3.3 _tInstruction Set _g353 -- _g14.3.4 _tHDL Generation _g354
650		0	_aEmbedded computer systems.
650		0	_aEmbedded computer systems _xDesign and construction.
700	1		_aIenne, Paolo.
700	1		_aLeupers, Rainer.
830		0	_aMorgan Kaufmann series in systems on silicon.
856	4	2	_3Publisher description _uhttp://catdir.loc.gov/catdir/enhancements/fy0713/2007296561-d.html
942			_cBOOK
994			_aZ0 _bSUPMU
596			_a1 2
999			_c2379 _d2379