000			02949cam a22003614a 4500
001			u6887
003			SA-PMU
005			20210418122851.0
008			010119s2001 nyua b 001 0 eng
010			_a 2001017653
040			_aDLC _beng _cDLC _dUKM _dC#P _dBAKER _dBTCTA _dYDXCP _dOCLCG _dIG# _dDEBBG _dEXW _dOCLCQ _dBDX
020			_a0471412090 (cloth : alk. paper)
020			_a9780471412090 (cloth : alk. paper)
035			_a(OCoLC)45806404 _z(OCoLC)48931855
042			_apcc
050	0	0	_aTK7895.A65 _bF59 2001
082	0	0	_a004/.01/513 _221
100	1		_aFlynn, M. J. _q(Michael J.), _d1934-
245	1	0	_aAdvanced computer arithmetic design / _cMichael J. Flynn, Stuart F. Oberman.
260			_aNew York : _bJ. Wiley, _cc2001.
300			_axv, 325 p. : _bill. ; _c24 cm.
500			_a"A Wiley-Interscience publication."
504			_aIncludes bibliographical references (p. 309-319) and index.
505	0	0	_tInteger Addition -- _tRipple Adders; Manchester Carry Chain -- _tCarry Skip Adders; Multilevel Carry Skip -- _tCarry-Select and Conditional-Sum Adders -- _tCarry Lookahead Adders; Canonic Adders -- _tLing Adders -- _tAdder Implementations -- _tAn ECL Ling Adder -- _tGroup Generates -- _tLookahead Network -- _tFinal Sum -- _tCritical Path -- _tImplementation -- _tA CMOS Ling Adder -- _tGroup Generates -- _tLookahead Network -- _tFinal Sum -- _tCritical Path -- _tImplementation -- _tFloating-Point Addition -- _tImproved Algorithms for High-Speed FP Addition -- _tA Brief Review of FP Addition Algorithms (A1 and A2) -- _tA New Algorithm: A3 (Two Path with Integrated Rounding) -- _tVariable-Latency FP Addition -- _tVariable-Latency Algorithm -- _tTwo-Cycle Algorithm -- _tOne-Cycle Algorithm -- _tPerformance Results -- _tMultiplication with Partially Redundant Multiples -- _tAdd and Shift -- _tDot Diagrams -- _tBooth's Algorithm -- _tBooth 3 -- _tBooth 4 and Higher -- _tRedundant Booth -- _tBooth 3 with Fully Redundant Partial Products -- _tBooth 3 with Partially Redundant Partial Products -- _tDealing with Negative Partial Products -- _tBooth with Bias -- _tChoosing the Right Constant -- _tProducing the Multiples -- _tRedundant Booth 3 -- _tRedundant Booth 4 -- _tChoosing the Adder Length -- _tMultiplier Topologies -- _tReview of Issues in Partial-Product Summation -- _tRegular Topologies -- _tArray Topologies -- _tTree Topologies -- _tEffects of the Number of Tracks per Channel -- _tIrregular Topologies -- _tWallace Tree -- _tAlgorithmic Generation -- _tTechnology Scaling Effects on Multipliers.
650		0	_aComputer arithmetic and logic units.
700	1		_aOberman, Stuart F., _d1971-
856	4	2	_3Contributor biographical information _uhttp://catdir.loc.gov/catdir/bios/wiley043/2001017653.html
856	4	2	_3Publisher description _uhttp://catdir.loc.gov/catdir/description/wiley036/2001017653.html
856	4		_3Table of Contents _uhttp://catdir.loc.gov/catdir/toc/onix07/2001017653.html
942			_cBOOK
994			_aZ0 _bSUPMU
596			_a1 2
999			_c253 _d253