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008			990830s2000 caua b 001 0 eng
010			_a 99066780
040			_aDLC _beng _cDLC _dUKM _dZCU _dYDXCP _dBAKER _dOCLCG _dIG# _dZWZ _dUWW _dUKV3G _dBTCTA _dNUI _dDEBBG _dOCLCQ _dOCLCA _dOCLCQ _dBDX _dOCLCF _dOCLCO
020			_a0126912955 (alk. paper)
020			_a9780126912951 (alk. paper)
020			_a0126912963 (CD-ROM)
020			_a9780126912968 (CD-ROM)
035			_a(OCoLC)42622166 _z(OCoLC)59408128 _z(OCoLC)148698223
042			_apcc
050	0	0	_aTK7868.D5 _bT56 2000
082	0	0	_a621.39/5 _221
100	1		_aTinder, Richard F. _q(Richard Franchere), _d1930-2011.
245	1	0	_aEngineering digital design / _cby Richard F. Tinder.
250			_a2nd ed.
260			_aSan Diego : _bAcademic Press, _cc2000.
300			_ax xvi, 884 p. : _bill. ; _c26 cm. + _e1 computer optical disc (4 3/4 in.)
500			_aRev. ed. of: Digital engineering design. c1991.
504			_aIncludes bibliographical references and index.
538			_aSystem requirements for accompanying CD-ROM: Contains an instructor's manual giving the solutions of all end-of-chapter problems, a logic minimization program called BOOZER which operates in the DOS mode on conventional PCs, and an interactive logic simulator called EXL-Sim2000 which operates in the Windows environment and requires little computer memory.
505	0		_aIntroductory remarks and glossary -- Number systems, binary arithmetic, and codes -- Background for digital design -- Logic function representation and minimization -- Function minimization by using K-map XOR patterns and Reed-Muller transformation forms -- Nonarithmetic combinational logic devices -- Programmable logic devices -- Arithmetic devices and arithmetic logic units (ALUs) -- Propagation delay and timing defects in combinational logic -- Introduction to synchronous state machine design and analysis -- Synchronous FSM design considerations and applications -- Module and bit-slice devices -- Alternative synchronous FSM architectures and systems-level design -- Asynchronous state machine design and analysis: basic concepts -- The pulse mode approach to asynchronous FSM design -- Externally asynchronous/internally clocked (pausable) systems and programmable asynchronous sequencers -- Other transistor logic families -- Computer-aided engineering tools -- IEEE Standard symbols.
650		0	_aDigital electronics.
650		0	_aLogic design.
700	1		_aTinder, Richard F. _q(Richard Franchere), _d1930-2011. _tDigital engineering design.
856	4	1	_3Table of contents _uhttp://catdir.loc.gov/catdir/toc/els033/99066780.html
856	4	2	_3Publisher description _uhttp://catdir.loc.gov/catdir/description/els033/99066780.html
942			_cBOOK
994			_aZ0 _bSUPMU
596			_a1 2
999			_c3534 _d3534