000			03010cam a22003494a 4500
001			u8817
003			SA-PMU
005			20210418123833.0
008			040303s2004 njua bf 001 0 eng
010			_a 2004046509 _z 2004105832
040			_aDLC _beng _cDLC _dMUQ _dBAKER _dUKM _dBTCTA _dYDXCP _dUQ1 _dIG# _dDEBBG _dUKMGB _dBDX _dUMR _dOCLCF
020			_a013142291X
020			_a9780131422919
035			_a(OCoLC)54753180 _z(OCoLC)56447118
042			_apcc
050	0	0	_aTK5102.9 _b.G72 2004
082	0	0	_a621.382/2 _222
100	1		_aGranberg, Tom, _d1949-
245	1	0	_aHandbook of digital techniques for high-speed design : _bdesign examples, signaling and memory technologies, fiber optics, modeling and simulation to ensure signal integrity / _cTom Granberg.
260			_aUpper Saddle River, NJ : _bPrentice Hall PTR, _c2004.
300			_axliv, 928 p. : _bill. ; _c24 cm.
490	1		_aPrentice Hall modern semiconductor design series
504			_aIncludes bibliographical references and index.
505	0		_aTrends in High-Speed Design -- ASICs, Backplane Configurations, and SerDes Technology -- A Few Basics on Signal Integrity -- Gunning Transceiver Logic (GTL, GTLP, GTL+, AGTL+) -- Low Voltage Differential Signaling (LVDS) -- Bus VLDS (BLVDS), LVDS Multipoint (LVDM), and Multipoint LVDS (M-LVDS) -- High-Speed Transceiver Logi (HSTL) and Sub-Series Terminated Logic (SSTL) -- Emitter Coupled Logic (ECL, PECL, LVPECL, ECLinPS Lite and Plus, SiGe, ECL Pro, GigaPro and GigaComm) -- Current-Mode Logic (CML) -- FPGAs - 11.1Gbps RocketIOs and HardCopy Devices -- Fiber-Optic Components -- High-Speed Interconnects and Cabling -- Memory Device Overview and Memory Signaling Technologies -- Double Data Rate SDRAM (DDR, DDR2) and SPICE Simulation -- GDDR3, ZBT, FCRAM, SigmaRAM, RLDRAM, DDR SRAM, Flash, FeRAM, and MRAM -- Quad Data Rate (QDR, QDRII) SRAM -- Direct Rambus DRAM (DRDRAM) -- Xtreme Data Rate (XDR) DRAM, FlexPhase and ODR -- Differential and Mixed-Mode S-Parameters -- Time Domain Reflectometry (TDR), Time Domain Transmission (TDT), and VNAs -- Modeling with IBIS -- Mentor Graphics - EDA Tools for High-Speed Design, Simulation, Verification, and Layout -- Advances in Design, Modeling, Simulation, and Measurement Validation of High-Performance Board-to-Board 5-10 Gbps Interconnects -- IBIS Modeling and Simulation of High-Speed Fiber-Optic Transceivers -- Design with LVDS -- Designing to 10 Gbps Using SerDes Transceivers, Serializers, and Deserializers -- WarpLink SerDes System Design Example -- Electrical Optical Circuit Board (EOCB) -- RapidIO -- PCI Express and ExpressCard -- Electrical and Optical Test Equipment.
650		0	_aSignal processing _xDigital techniques _vHandbooks, manuals, etc.
650		0	_aVery high speed integrated circuits _xDesign and construction _vHandbooks, manuals, etc.
650		0	_aSignal integrity (Electronics)
830		0	_aPrentice Hall modern semiconductor design series.
942			_cBOOK
994			_aZ0 _bSUPMU
596			_a1
999			_c4889 _d4889